公开(公告)号：CA2271536C

公开(公告)日：2002-07-02

申请号：CA2271536

申请日：1999-05-12

Applicant: IBM

Inventor： IACHETTA RICHARD N JR ,  DEAN MARK E ,  GLASCO DAVID B ,  CARPENTER GARY D

IPC: G06F15/177 ,  G06F12/08 ,  G06F13/38 ,  G06F15/17 ,  G06F12/02 ,  G06F15/167

Abstract: A non-uniform memory access (NUMA) computer system includes an interconnect to which multiple processing nodes (including first, second, and third processing nodes) are coupled. Each of the first, second, and third processing nodes includes at least one processor and a local system memory. The NUMA computer system further includes a transaction buffer, coupled to the interconnect, that stores communication transactions transmitted on the interconnect that are both initiated by and targeted at a processing node other than the third processi ng node. In response to a determination that a particular communication transaction originally targeting another processing node should be processed by the third processing node, buffer control logic coupled to the transaction buffer causes the particular communication transaction to be retrieved from the transaction buffer and processed by the third processing node. In one embodiment, the interconnect includes a broadcast fabric, and the transaction buffer and buffer control logic form a portion of the third processing node.

公开(公告)号：CA2271536A1

公开(公告)日：1999-12-30

申请号：CA2271536

申请日：1999-05-12

Applicant: IBM

Inventor： DEAN MARK E ,  GLASCO DAVID B ,  IACHETTA RICHARD N JR ,  CARPENTER GARY D

IPC: G06F15/177 ,  G06F12/08 ,  G06F13/38 ,  G06F15/17 ,  G06F12/02 ,  G06F15/167

Abstract: A non-uniform memory access (NUMA) computer system includes an interconnect to which multiple processing nodes (including first, second, and third processing nodes) are coupled. Each of the first, second, and third processing nodes includes at least one processor and a local system memory. The NUMA computer system further includes a transaction buffer, coupled to the interconnect, that stores communication transactions transmitted on the interconnect that are both initiated by and targeted at a processing node other than the third processing node. In response to a determination that a particular communication transaction originally targeting another processing node should be processed by the third processing node, buffer control logic coupled to the transaction buffer causes the particular communication transaction to be retrieved from the transaction buffer and processed by the third processing node. In one embodiment, the interconnect includes a broadcast fabric, and the transaction buffer and buffer control logic form a portion of the third processing node.

公开(公告)号：CA2295403A1

公开(公告)日：2000-08-10

申请号：CA2295403

申请日：2000-01-13

Applicant: IBM

Inventor： GLASCO DAVID B ,  DEAN MARK E ,  CARPENTER GARY D

IPC: G06F12/08 ,  G06F15/173

Abstract: A non-uniform memory access (NUMA) computer system includes first and second processing nodes that are each coupled to a node interconnect. The first processing node includes a system memory and first and second processors that each have a respective one of first and second cache hierarchies, which are coupled for communication by a local interconnect. The second processing node includes at least a system memory and a third processor having a third cache hierarchy. The first cache hierarchy and the third cache hierarchy are permitted to concurrently store an unmodified copy of a particular cache line in a Recent coherency state from which the copy of the particular cache line can be sourced by shared intervention. In response to a request for the particular cache line by the second cache hierarchy, the first cache hierarchy sources a copy of the particular cache line to the second cache hierarchy by shared intervention utilizing communication on only the local interconnect and without communication on the node interconnect.