公开(公告)号：JP2000112910A

公开(公告)日：2000-04-21

申请号：JP18183999

申请日：1999-06-28

Applicant: IBM

Inventor： CARPENTER GARY D ,  MARK EDWARD DEAN ,  DAVID BRIAN GLASCO ,  RICHARD NICHOLAS ACHETTA JR

IPC: G06F15/177 ,  G06F12/08 ,  G06F13/38 ,  G06F15/17

Abstract: PROBLEM TO BE SOLVED: To provide a nonuniform memory access(NUMA) computer system having a short inter-node communication waiting duration by providing a buffer control logic or the like for extracting a specified communication transaction from a transaction buffer and processing it by a third processing node. SOLUTION: This NUMA computer system 8 is provided with the transaction buffer connected to a mutual connecting means. This transaction buffer stores a communication transaction which defines the processing node excepting for a third processing node 10c as the destination (target). Corresponding to the determination to process the specified communication transaction, which originally defines the other processing node as the destination, by the third processing node 10c, the buffer control logic connected to the transaction buffer extracts the specified communication transaction from the transaction buffer and the transaction is processed by the third processing node 10c.

公开(公告)号：JP2000242621A

公开(公告)日：2000-09-08

申请号：JP2000031050

申请日：2000-02-08

Applicant: IBM

Inventor： CARPENTER GARY D ,  MARK EDWARD DEAN ,  DAVID BRIAN GLASCO

IPC: G06F12/08 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To reduce the number of readout requests and wait time of the nonuniform memory access computer system by interposing a 1st cache hierarchy in common and using only communication through local interconnection, and sending a copy of a specific cache line to a 2nd cache hierarchy. SOLUTION: When the 1st cache hierarchy 14 as a request source receives a request cache line through local interconnection 16, a cache controller of the 2nd cache hierarchy 14 caches the request cache line and sets its coherence state to a (Recent) state. Namely, the 1st cache hierarchy 14 as the request source among local cache hierarchy 14 holding the request cache line is interposed in common and only the communication by the local interconnection 16 is used to send a copy of the specific cache line to the 2nd cache hierarchy 14.

公开(公告)号：JP2002278921A

公开(公告)日：2002-09-27

申请号：JP2002074116

申请日：2002-03-18

Applicant: IBM

Inventor： BEAMAN DANIEL PAUL ,  CARPENTER GARY D ,  MARK EDWARD DEAN ,  VOIGT WENDEL GLENN

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/40

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for arbitrating bus control between a first bus master having a two-way handshake bus acquirement protocol and a second bus master having a one-way bus acquirement protocol. SOLUTION: The method and system for arbitrating the two bus masters having the two different bus acquirement protocols are provided. The control of a bus is taken up from the first bus master in response to the output of a bus request by the second bus master when the first bus master controls the bus. When an arbitration controller transmits a signal for ordering the first bus master to terminate a bus transaction, the control of the bus is given to the second bus master. When the second bus master terminates the bus request, the control of the bus is given to the first bus master and a signal for confirming the permission of control is transmitted from the arbitration controller to the first bus master.

公开(公告)号：JP2004199664A

公开(公告)日：2004-07-15

申请号：JP2003394561

申请日：2003-11-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CARPENTER GARY D ,  CHANDRA VIKAS

IPC: G06F1/06 ,  G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  G06F1/24 ,  G06F13/364 ,  H04L12/28

CPC classification number: G06F1/24 ,  G06F1/08 ,  G06F1/10 ,  G06F1/12 ,  G06F13/364

Abstract: PROBLEM TO BE SOLVED: To solve problems which are necessary to improve flexibility of operating frequencies of a synchronous bus. SOLUTION: In one mode of this invention, the method for communicating between subsystems coupled to a bus of a computer system on an integrated circuit chip includes a step which makes the subsystems operate by independent clock frequencies when the subsystems do not communicate each other through the bus. A selected pair of the subsystems is made to operate by a shared clock frequency by selectively varying the frequency of a clock signal supplied to the subsystems, and the selected subsystems are enabled to communicate each other by the shared clock frequency through the bus (The clock frequency is different when the pair of subsystems is different.); and the subsystem are made to enable to operate by an independent clock frequency when the subsystem does not communicate to other subsystem. Communication between subsystems is performed by bus-based protocol; as the result, when a subsystem is permitted to access to the bus, the subsystem can use the bus exclusively. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2002182803A

公开(公告)日：2002-06-28

申请号：JP2001301550

申请日：2001-09-28

Applicant: IBM

Inventor： BROCK BISHOP C ,  CARPENTER GARY D ,  NOWKA KEVIN J

IPC: G06F1/30 ,  G06F1/00 ,  G06F1/24 ,  G06F11/00 ,  G06F12/16 ,  G06F13/24

Abstract: PROBLEM TO BE SOLVED: To provide a resumption function of a computer system after an integrated circuit in the battery type computer system is disconnected completely in a method and a device for keeping the state of a computer system component. SOLUTION: The state is read by using a scanning latch in the computer system component. A scanning register can be accessed internally through internal scan chaining or externally by using a serial test port interface or a boundary scan interface. Next, the state is stored in a nonvolatile storage area, and the power is disconnected from the computer system component.

公开(公告)号：CA2295403A1

公开(公告)日：2000-08-10

申请号：CA2295403

申请日：2000-01-13

Applicant: IBM

Inventor： GLASCO DAVID B ,  DEAN MARK E ,  CARPENTER GARY D

IPC: G06F12/08 ,  G06F15/173

Abstract: A non-uniform memory access (NUMA) computer system includes first and second processing nodes that are each coupled to a node interconnect. The first processing node includes a system memory and first and second processors that each have a respective one of first and second cache hierarchies, which are coupled for communication by a local interconnect. The second processing node includes at least a system memory and a third processor having a third cache hierarchy. The first cache hierarchy and the third cache hierarchy are permitted to concurrently store an unmodified copy of a particular cache line in a Recent coherency state from which the copy of the particular cache line can be sourced by shared intervention. In response to a request for the particular cache line by the second cache hierarchy, the first cache hierarchy sources a copy of the particular cache line to the second cache hierarchy by shared intervention utilizing communication on only the local interconnect and without communication on the node interconnect.

公开(公告)号：CA2271536A1

公开(公告)日：1999-12-30

申请号：CA2271536

申请日：1999-05-12

Applicant: IBM

Inventor： DEAN MARK E ,  GLASCO DAVID B ,  IACHETTA RICHARD N JR ,  CARPENTER GARY D

IPC: G06F15/177 ,  G06F12/08 ,  G06F13/38 ,  G06F15/17 ,  G06F12/02 ,  G06F15/167

Abstract: A non-uniform memory access (NUMA) computer system includes an interconnect to which multiple processing nodes (including first, second, and third processing nodes) are coupled. Each of the first, second, and third processing nodes includes at least one processor and a local system memory. The NUMA computer system further includes a transaction buffer, coupled to the interconnect, that stores communication transactions transmitted on the interconnect that are both initiated by and targeted at a processing node other than the third processing node. In response to a determination that a particular communication transaction originally targeting another processing node should be processed by the third processing node, buffer control logic coupled to the transaction buffer causes the particular communication transaction to be retrieved from the transaction buffer and processed by the third processing node. In one embodiment, the interconnect includes a broadcast fabric, and the transaction buffer and buffer control logic form a portion of the third processing node.

公开(公告)号：CA2271536C

公开(公告)日：2002-07-02

申请号：CA2271536

申请日：1999-05-12

Applicant: IBM

Inventor： IACHETTA RICHARD N JR ,  DEAN MARK E ,  GLASCO DAVID B ,  CARPENTER GARY D

IPC: G06F15/177 ,  G06F12/08 ,  G06F13/38 ,  G06F15/17 ,  G06F12/02 ,  G06F15/167

Abstract: A non-uniform memory access (NUMA) computer system includes an interconnect to which multiple processing nodes (including first, second, and third processing nodes) are coupled. Each of the first, second, and third processing nodes includes at least one processor and a local system memory. The NUMA computer system further includes a transaction buffer, coupled to the interconnect, that stores communication transactions transmitted on the interconnect that are both initiated by and targeted at a processing node other than the third processi ng node. In response to a determination that a particular communication transaction originally targeting another processing node should be processed by the third processing node, buffer control logic coupled to the transaction buffer causes the particular communication transaction to be retrieved from the transaction buffer and processed by the third processing node. In one embodiment, the interconnect includes a broadcast fabric, and the transaction buffer and buffer control logic form a portion of the third processing node.