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    DIGITAL SIGNAL PROCESSOR WITH CASCADED SIMD ORGANIZATION
    1.
    发明申请
    DIGITAL SIGNAL PROCESSOR WITH CASCADED SIMD ORGANIZATION 审中-公开
    具有级联SIMD组织的数字信号处理器

    公开(公告)号：WO2004004191A3

    公开(公告)日：2004-04-29

    申请号：PCT/US0320102

    申请日：2003-06-24

    Applicant: IBM

    Inventor： GLOSSNER CLAIR JOHN III ,  HOKENEK ERDEM ,  MELTZER DAVID ,  MOUDGILL MAYAN

    IPC: G06F9/345 ,  G06F15/78 ,  G06F15/80 ,  G06F15/76

    CPC classification number: G06F15/8084 ,  G06F9/345 ,  G06F9/3455 ,  G06F9/3887 ,  G06F15/8076 ,  G06F15/8092

    Abstract: A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e.g., its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.

    Abstract translation: 数字信号处理器（DSP）包括级联连接的双SIMD单元，并且级联的第一SIMD级的结果可以存储在级联中的第二SIMD级的寄存器文件中。 每个SIMD级包含其自己的用于存储操作数和中间结果（例如，它自己的寄存器文件）的资源，以及用于解码可能在该阶段中执行的操作。 在每个阶段中，硬件资源被组织为以SIMD方式操作，以便可以同时执行独立的SIMD操作，级联的每个阶段都有一个操作。 流经级联的中间操作数和结果存储在阶段的寄存器文件中，并且可以从这些寄存器文件访问。 数据也可能直接从内存中导入级联中的阶段的寄存器文件中。

    VECTOR REGISTER FILE WITH ARBITRARY VECTOR ADDRESSING
    2.
    发明专利
    VECTOR REGISTER FILE WITH ARBITRARY VECTOR ADDRESSING 未知

    公开(公告)号：CA2337784A1

    公开(公告)日：2001-08-29

    申请号：CA2337784

    申请日：2001-02-15

    Applicant: IBM

    Inventor： GLOSSNER CLAIR JOHN III ,  HOKENEK ERDEM ,  MELTZER DAVID ,  MOUDGILL MAVAN

    IPC: G06F17/16 ,  G06F9/345 ,  G06F12/00 ,  G06F15/78 ,  G06F15/80

    Abstract: A system and method for processing operations that use data vectors each comprising a plurality of data elements, in accordance with the present invention, includ es a vector data file comprising a plurality of storage elements for storing data elements of the data vectors. A pointer array is coupled by a bus to the vector data file. The pointer array includes a plurality of entries wherein each entry identifies at least one storage element in the vector data file. The at least one storage element stores at least one data element of the data vectors, wherein for at least one particular entry in the pointer array, the at least one storage element identified by the particular entry has an arbitrary starting address in the vector data file.

    Digital signal processor with cascaded simd organization
    4.
    发明专利
    Digital signal processor with cascaded simd organization 未知

    公开(公告)号：AU2003249378A8

    公开(公告)日：2004-01-19

    申请号：AU2003249378

    申请日：2003-06-24

    Applicant: IBM

    Inventor： MELTZER DAVID ,  HOKENEK ERDEM ,  MOUDGILL MAYAN ,  GLOSSNER CLAIR JOHN III

    IPC: G06F9/345 ,  G06F15/78 ,  G06F15/80 ,  G06F15/76

    Abstract: A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e.g., its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.

    DIGITAL SIGNAL PROCESSOR WITH CASCADED SIMD ORGANIZATION
    6.
    发明专利
    DIGITAL SIGNAL PROCESSOR WITH CASCADED SIMD ORGANIZATION 未知

    公开(公告)号：AU2003249378A1

    公开(公告)日：2004-01-19

    申请号：AU2003249378

    申请日：2003-06-24

    Applicant: IBM

    Inventor： MELTZER DAVID ,  MOUDGILL MAYAN ,  GLOSSNER CLAIR JOHN III ,  HOKENEK ERDEM

    IPC: G06F9/345 ,  G06F15/78 ,  G06F15/80

    Abstract: A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e.g., its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.

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