公开(公告)号：EP0767424A3

公开(公告)日：1998-10-21

申请号：EP96306526

申请日：1996-09-09

Applicant: IBM

Inventor： ENGEBRETSEN DAVID ROBERT ,  GREGOR STEVEN LEE ,  MOUDGILL MAYAN ,  WILLIS JOHN CHRISTOPHER

IPC: G06F9/34 ,  G06F9/30 ,  G06F9/35 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F9/3013 ,  G06F9/35 ,  G06F9/383

Abstract: A processor (20) includes an alias unit (30) having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries (34) that consist of a base address in the processor memory (24) to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor (20) can optionally include a data cache (28) and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.

公开(公告)号：AU2003249378A8

公开(公告)日：2004-01-19

申请号：AU2003249378

申请日：2003-06-24

Applicant: IBM

Inventor： MELTZER DAVID ,  HOKENEK ERDEM ,  MOUDGILL MAYAN ,  GLOSSNER CLAIR JOHN III

IPC: G06F9/345 ,  G06F15/78 ,  G06F15/80 ,  G06F15/76

Abstract: A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e.g., its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.

公开(公告)号：CA2481567A1

公开(公告)日：2003-10-30

申请号：CA2481567

申请日：2002-04-19

Applicant: IBM

Inventor： ALTMAN ERIK R ,  MOUDGILL MAYAN ,  GLOSSNER CLAIR JOHN III ,  MELTZER DAVID ,  HOKENEK ERDEM

IPC: G06F1/32 ,  G06F9/45 ,  G06F15/78

Abstract: A microprocessor includes a logic circuit. A selection device is coupled to the logic circuit, and the selection device procides switching of on/off states of the logic circuit based on a stored logical value. A program instruction is included which sets the stored logical value control the on/o ff states of the logic circuit based on anticipated usage of the logical circui t in accordance with an instruction sequence of the microprocessor.

公开(公告)号：HK1016291A1

公开(公告)日：1999-10-29

申请号：HK99101156

申请日：1999-03-23

Applicant: IBM

Inventor： MORENO JAIME UMBERTO ,  MOUDGILL MAYAN

IPC: G06F9/38 ,  G06F

Abstract: The present invention is an apparatus that maps the memory address space of the computer system into regions, and detects the incorrect execution of a load operation performed earlier than a sequentially preceding (in program order) store operation. The apparatus detects out-of-order load operations, uses a region-based mapping table to keep track of the memory regions accessed by the out-of-order load operations, detects the execution of store operations into regions accessed by out-of-order load operations, and generates a program exception when interference among reordered operations is detected. The invention is applicable to static and dynamic reordering of memory operations.

公开(公告)号：WO2004004191A3

公开(公告)日：2004-04-29

申请号：PCT/US0320102

申请日：2003-06-24

Applicant: IBM

Inventor： GLOSSNER CLAIR JOHN III ,  HOKENEK ERDEM ,  MELTZER DAVID ,  MOUDGILL MAYAN

IPC: G06F9/345 ,  G06F15/78 ,  G06F15/80 ,  G06F15/76

CPC classification number: G06F15/8084 ,  G06F9/345 ,  G06F9/3455 ,  G06F9/3887 ,  G06F15/8076 ,  G06F15/8092

Abstract: A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e.g., its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.

Abstract translation: 数字信号处理器（DSP）包括级联连接的双SIMD单元，并且级联的第一SIMD级的结果可以存储在级联中的第二SIMD级的寄存器文件中。 每个SIMD级包含其自己的用于存储操作数和中间结果（例如，它自己的寄存器文件）的资源，以及用于解码可能在该阶段中执行的操作。 在每个阶段中，硬件资源被组织为以SIMD方式操作，以便可以同时执行独立的SIMD操作，级联的每个阶段都有一个操作。 流经级联的中间操作数和结果存储在阶段的寄存器文件中，并且可以从这些寄存器文件访问。 数据也可能直接从内存中导入级联中的阶段的寄存器文件中。

公开(公告)号：DE69620702T2

公开(公告)日：2003-04-03

申请号：DE69620702

申请日：1996-09-09

Applicant: IBM

Inventor： ENGEBRETSEN DAVID ROBERT ,  GREGOR STEVEN LEE ,  MOUDGILL MAYAN ,  WILLIS JOHN CHRISTOPHER

IPC: G06F9/34 ,  G06F9/30 ,  G06F9/35 ,  G06F9/38 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10

Abstract: A processor (20) includes an alias unit (30) having high-speed memory storage locations allocated at compile time for variable-sized data objects. The storage locations are accessed through a table of alias entries (34) that consist of a base address in the processor memory (24) to which the alias entry is aliased, the number of bytes in the alias entry, and a base address that points to the first byte of alias buffer memory representing the value of the alias entry. Each alias entry is given a unique name from a small name space that is encoded into relevant machine opcodes. The names are used to reference the data objects. The processor (20) can optionally include a data cache (28) and can be used in either single processor or multi-tasking environments. Reference to a memory location address associated with an alias register entry would be redirected to the intermediate storage.

公开(公告)号：GB2324181B

公开(公告)日：2001-11-21

申请号：GB9803608

申请日：1998-02-21

Applicant: IBM

Inventor： MORENO JAIME UMBERTO ,  MOUDGILL MAYAN

IPC: G06F9/38

Abstract: The present invention is an apparatus that maps the memory address space of the computer system into regions, and detects the incorrect execution of a load operation performed earlier than a sequentially preceding (in program order) store operation. The apparatus detects out-of-order load operations, uses a region-based mapping table to keep track of the memory regions accessed by the out-of-order load operations, detects the execution of store operations into regions accessed by out-of-order load operations, and generates a program exception when interference among reordered operations is detected. The invention is applicable to static and dynamic reordering of memory operations.

公开(公告)号：BR9800961A

公开(公告)日：1999-10-19

申请号：BR9800961

申请日：1998-03-25

Applicant: IBM

Inventor： MORENO JAIME HUMBERTO ,  MOUDGILL MAYAN

IPC: G06F9/38 ,  G06F11/25

Abstract: The present invention is an apparatus that maps the memory address space of the computer system into regions, and detects the incorrect execution of a load operation performed earlier than a sequentially preceding (in program order) store operation. The apparatus detects out-of-order load operations, uses a region-based mapping table to keep track of the memory regions accessed by the out-of-order load operations, detects the execution of store operations into regions accessed by out-of-order load operations, and generates a program exception when interference among reordered operations is detected. The invention is applicable to static and dynamic reordering of memory operations.

公开(公告)号：AU2003249378A1

公开(公告)日：2004-01-19

申请号：AU2003249378

申请日：2003-06-24

Applicant: IBM

Inventor： MELTZER DAVID ,  MOUDGILL MAYAN ,  GLOSSNER CLAIR JOHN III ,  HOKENEK ERDEM

IPC: G06F9/345 ,  G06F15/78 ,  G06F15/80

Abstract: A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e.g., its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.

公开(公告)号：AU2002257172A1

公开(公告)日：2003-11-03

申请号：AU2002257172

申请日：2002-04-19

Applicant: IBM

Inventor： GLOSSNER CLAIR JOHN III ,  HOKENEK ERDEM ,  MELTZER DAVID ,  MOUDGILL MAYAN ,  ALTMAN ERIK R

IPC: G06F1/32 ,  G06F9/45 ,  G06F15/78

Abstract: A microprocessor includes a logic circuit. A selection device is coupled to the logic circuit, and the selection device procides switching of on/off states of the logic circuit based on a stored logical value. A program instruction is included which sets the stored logical value control the on/off states of the logic circuit based on anticipated usage of the logical circuit in accordance with an instruction sequence of the microprocessor.