公开(公告)号：CA1095176A

公开(公告)日：1981-02-03

申请号：CA293904

申请日：1977-12-23

Applicant: IBM

Inventor： CRAMER CLARK E ,  GAETJEN JOHN R ,  GRANT CARL H ,  NELSON PAUL E ,  NEWLIN FRANK A III

IPC: G06F13/00 ,  G06F13/12 ,  G06F13/28 ,  G11C9/02

Abstract: DATA TRANSFER SYSTEM A method for accessing and storing data in randomly assigned storage locations in a memory associated with a processor under the control of external circuits connected to the processor I/0 bus, said external circuits being provided with registers for storing several assigned addresses in the memory which contain the starting addresses in the memory of a control list stored in a plurality of sequential addresses and five or more storage areas, each including a plurality of contiguous storage locations and further provision being made within the said processor for incrementing the addresses stored in the said assigned addresses each time they are accessed for performing a reading or writing operation in the memory location designated therein.

公开(公告)号：CA1115850A

公开(公告)日：1982-01-05

申请号：CA334531

申请日：1979-08-24

Applicant: IBM

Inventor： ADAMS ROBERT L JR ,  GRANT CARL H ,  STEVENS KARL W

IPC: G06F13/12 ,  G06F9/46 ,  G06F13/34

Abstract: An improved I/O interrupt sequencing method and apparatus including generation of an instruction priority request signal to indicate that a real time task requires programmed I/O service. Generating an end of chain signal to suspend burst I/O control of the I/O bus and allow programmed I/O service to a real time device, and resetting the instruction priority request signal to allow burst mode data transfer to continue at the count positions at which it was suspended. KI9-78-0066

公开(公告)号：FR2379113A1

公开(公告)日：1978-08-25

申请号：FR7737954

申请日：1977-12-09

Applicant: IBM

Inventor： CRAMER CLARK E ,  GAETJEN JOHN R ,  GRANT CARL H ,  NELSON PAUL E ,  NEWLIN FRANK A III

IPC: G06F13/00 ,  G06F13/12 ,  G06F13/28 ,  G06F3/04

Abstract: A method for accessing and storing data in randomly assigned storage locations in a memory associated with a processor under the control of external circuits connected to the processor I/O bus, said external circuits being provided with registers for storing several assigned addresses in the memory which contain the starting addresses in the memory of a control list stored in a plurality of sequential addresses and five or more storage areas, each including a plurality of contiguous storage locations and further provision being made within the said processor for incrementing the addresses stored in the said assigned addresses each time they are accessed for performing a reading or writing operation in the memory location designated therein.