公开(公告)号：FR2379113A1

公开(公告)日：1978-08-25

申请号：FR7737954

申请日：1977-12-09

Applicant: IBM

Inventor： CRAMER CLARK E ,  GAETJEN JOHN R ,  GRANT CARL H ,  NELSON PAUL E ,  NEWLIN FRANK A III

IPC: G06F13/00 ,  G06F13/12 ,  G06F13/28 ,  G06F3/04

Abstract: A method for accessing and storing data in randomly assigned storage locations in a memory associated with a processor under the control of external circuits connected to the processor I/O bus, said external circuits being provided with registers for storing several assigned addresses in the memory which contain the starting addresses in the memory of a control list stored in a plurality of sequential addresses and five or more storage areas, each including a plurality of contiguous storage locations and further provision being made within the said processor for incrementing the addresses stored in the said assigned addresses each time they are accessed for performing a reading or writing operation in the memory location designated therein.

公开(公告)号：CA1095176A

公开(公告)日：1981-02-03

申请号：CA293904

申请日：1977-12-23

Applicant: IBM

Inventor： CRAMER CLARK E ,  GAETJEN JOHN R ,  GRANT CARL H ,  NELSON PAUL E ,  NEWLIN FRANK A III

IPC: G06F13/00 ,  G06F13/12 ,  G06F13/28 ,  G11C9/02

Abstract: DATA TRANSFER SYSTEM A method for accessing and storing data in randomly assigned storage locations in a memory associated with a processor under the control of external circuits connected to the processor I/0 bus, said external circuits being provided with registers for storing several assigned addresses in the memory which contain the starting addresses in the memory of a control list stored in a plurality of sequential addresses and five or more storage areas, each including a plurality of contiguous storage locations and further provision being made within the said processor for incrementing the addresses stored in the said assigned addresses each time they are accessed for performing a reading or writing operation in the memory location designated therein.

公开(公告)号：CA985424A

公开(公告)日：1976-03-09

申请号：CA159299

申请日：1972-12-18

Applicant: IBM

Inventor： BELL NOEL J ,  COOPER RONALD J ,  NAGLE FREDERICK P ,  NEWLIN FRANK A III ,  STADLER WILLIAM M

IPC: H03M7/02 ,  G06F5/00 ,  G06F13/00 ,  H03M5/00 ,  H04L13/06 ,  H04L17/30

Abstract: The described apparatus is interposed between the modem or line adapter of a synchronous transmission line and the data processor and will identify for the processor, the code in which data is being received. The discriminator is particularly useful in a system where any one of a number of data terminals using different transmission codes can be connected to one of the ports of the processor. In use, the discriminator examines, at each bit time, the last grouping of bits it has received to detect the presence of a code identifying character. When it detects one such character, the system waits until another character is received to determine if the second character is consistent with the tentatively identified code. If not, the system resets to continue looking for a new identification character. The system continues hunting until a transmission code is fully identified. The discriminator then notifies the processor of the code in which the data is being received.