公开(公告)号：CA2007413C

公开(公告)日：1994-09-06

申请号：CA2007413

申请日：1990-01-09

Applicant: IBM

Inventor： FISCHER JEFFREY H ,  GRASSO LAWRENCE J ,  HOFFMAN DALE E ,  SKOOGLUND DANIEL E ,  YOUNG DIANE K

IPC: H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03K3/86

Abstract: A method of operating a delay circuit to impose a selected delay on an electronic signal, the delay circuit comprising a plurality of delay stages and means for directing the electronic signal through selected ones of the delay stages, the method compris? ing the steps of: measuring the actual signal delay through each of the delay stages; and selecting, based on the signal delays obtained in the measuring step, the delay stages through which the electronic signal is directed.

公开(公告)号：DE3477716D1

公开(公告)日：1989-05-18

申请号：DE3477716

申请日：1984-07-03

Applicant: IBM

Inventor： CHANG YIHUA E ,  GRASSO LAWRENCE J ,  GRUODIS ALGIRDAS J ,  MORGAN CARROLL E

IPC: G06F1/08 ,  H03K3/78 ,  H03K5/156 ,  H03K23/66 ,  H03K5/13

Abstract: A high-speed programmable timing generator in which a continuously cycling binary count is compared with an input data word. Predetermined bits, starting from the highest- order end of the counter (24), can be selectively inhibited by an inhibit word (M) to effectively vary the cycle period of the counter. The digital word (D) with which the output of the counter is compared can be varied to set the reference phase of the output timing pulse stream. Further, fine delay adjustment (23) of the phase of the output timing pulse stream is effected by a controllable phase-locked loop (22).