公开(公告)号：GB2343596A

公开(公告)日：2000-05-10

申请号：GB9824228

申请日：1998-11-06

Applicant: IBM

Inventor： GRAY MANDY ALEXANDER ,  PALMER MICHAEL J ,  JUDD IAN DAVID

IPC: H04L12/933 ,  H04L12/403 ,  G06F13/362

Abstract: For connecting together, in a VLSI chip, a plurality of macros which require data flow connections between each other, a simple standard interface is realised between all macros. Any number of macros can be connected together, also allowing concurrent transactions between 4 or more macros using a cross-bar switch. Each macro may be a master (capable of requesting connections), a slave (capable of receiving connections from a master) or both. The centralised inter-connect logic includes three major components: the cross-bar switch, which makes the connections between the macros, the address decoder, which determines which slave each master wishes to connect to and an arbiter, which arbitrates between the macros when two or more masters request a connection simultaneously.