1.
    发明专利
    未知

    公开(公告)号:DE2855946A1

    公开(公告)日:1979-07-05

    申请号:DE2855946

    申请日:1978-12-23

    Applicant: IBM

    Abstract: This specification discloses a multi digit binary adder embodied in programmable logic arrays (PLAs). The particular programmable logic array used here has a separate two bit decoder for receiving each like order pairs of digits Ai, Bi of two n digit binary numbers A0, A1....An-1 and B0, B1....Bn-1 plus a carry Cin. The decoders generate an output signal called a min term on a different line for each of the four possible combinations AiBi, AiBi, AiBi and AiBi of the true and complement of each pair. The min terms from the decoders are fed to an array called the product term generator or AND array which generates product terms FP=F0(A0,B0) f1(A1,B1)....fn-1(An-1, Bn-1) fn(Cin) The product terms are fed to a second array called a sum of product term generator or OR array that sums product terms fp. A series of latches is last in the sequence of logic elements making up the PLA. These latches each perform an AND function to generate a sum bit Si that is an AND of two functions supplied by the OR array to the inputs of the latches to generate a sum S0, S1....Sn-1 plus a carry Cout for the adder at the output of the PLA. The adder is optimized for a PLA with latches that perform an AND function.

    2.
    发明专利
    未知

    公开(公告)号:MX153861A

    公开(公告)日:1987-01-26

    申请号:MX19503282

    申请日:1982-11-03

    Applicant: IBM

    Abstract: A multiple user shared bus contention resolution facility permits processing elements (PE's) to communicate with other PE's entirely under the control of each PE without a separate bus controller. Each PE has means for broadcasting its priority code on a contention portion of the bus and for sampling the bus after a delay in which it has received the codes from other PE's. Each PE holds its priority code on the bus for a further delay during which other PE's can sample the priority code. The PE's resolve contention for access to the information portion of the bus in a multi stage contention sequence. System usage, made possible by peer-to-peer distribution of bus access control, includes dynamic driven priority schemes, a variety of operating modes and hence flexible multiplexing of message traffic.

    GRAPHIC OUTPUT SYSTEM
    3.
    发明专利

    公开(公告)号:DE3175685D1

    公开(公告)日:1987-01-15

    申请号:DE3175685

    申请日:1981-08-28

    Applicant: IBM

    Abstract: A graphic output system generates circular arcs of lengths up to and including a full circle of 360 degrees. Nonsymmetrical closest points are located for noninteger radius and arc center values. Incremental move commands are generated for drawing an arc either in the clockwise or counter clockwise direction which is a distinct advantage when used to drive a pen type electromechanical plotter. By dividing the generation of a 360 degree arc into eight octants, only two of the original eight directions need to be considered as candidate directions toward the next integer display matrix value to be displayed. Initialization provides a simple stopping test for any circular arc of arbitrary length and direction. Only simple addition and sign testing is used to display the circular arc.

    BUS CONTENTION RESOLUTION IN DATA PROCESSING APPARATUS HAVING MULTIPLE INDEPENDANT USERS

    公开(公告)号:DE3271388D1

    公开(公告)日:1986-07-03

    申请号:DE3271388

    申请日:1982-09-16

    Applicant: IBM

    Abstract: A multiple user shared bus contention resolution facility permits processing elements (PE's) to communicate with other PE's entirely under the control of each PE without a separate bus controller. Each PE has means for broadcasting its priority code on a contention portion of the bus and for sampling the bus after a delay in which it has received the codes from other PE's. Each PE holds its priority code on the bus for a further delay during which other PE's can sample the priority code. The PE's resolve contention for access to the information portion of the bus in a multi stage contention sequence. System usage, made possible by peer-to-peer distribution of bus access control, includes dynamic driven priority schemes, a variety of operating modes and hence flexible multiplexing of message traffic.

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