公开(公告)号：DE3881855T2

公开(公告)日：1993-12-23

申请号：DE3881855

申请日：1988-11-30

Applicant: IBM

Inventor： CHU ALBERT MANHEE ,  GRIFFIN WILLIAM ROBERT

IPC: H03H11/26 ,  H01L27/092 ,  H03K5/00 ,  H03K5/13

Abstract: A signal delay circuit is provided which includes first (16) and second (10) circuits connected in parallel with each other. The first circuit includes serially connected first (18) and second (20) transistors of a first conductivity type, and the second circuit includes serially connected third (12) and fourth (14) transistors of a conductivity type opposite to the first one. A fifth transistor (24) of the first conductivity type and a sixth one (26) of the opposite conductivity type are connected in parallel from the common point (B) provided between the first and second transistors to the common point (C) between the third and fourth transistors. A signal to be delayed is applied to one end of the parallely arranged first and second circuits, and a complementary signal to the control electrodes of the transistors.

公开(公告)号：DE3881855D1

公开(公告)日：1993-07-22

申请号：DE3881855

申请日：1988-11-30

Applicant: IBM

Inventor： CHU ALBERT MANHEE ,  GRIFFIN WILLIAM ROBERT

IPC: H03H11/26 ,  H01L27/092 ,  H03K5/00 ,  H03K5/13

Abstract: A signal delay circuit is provided which includes first (16) and second (10) circuits connected in parallel with each other. The first circuit includes serially connected first (18) and second (20) transistors of a first conductivity type, and the second circuit includes serially connected third (12) and fourth (14) transistors of a conductivity type opposite to the first one. A fifth transistor (24) of the first conductivity type and a sixth one (26) of the opposite conductivity type are connected in parallel from the common point (B) provided between the first and second transistors to the common point (C) between the third and fourth transistors. A signal to be delayed is applied to one end of the parallely arranged first and second circuits, and a complementary signal to the control electrodes of the transistors.

公开(公告)号：DE3485112D1

公开(公告)日：1991-10-31

申请号：DE3485112

申请日：1984-11-06

Applicant: IBM

Inventor： GRIFFIN WILLIAM ROBERT ,  HELLER LAWRENCE GRIFFITH

IPC: H01L21/8238 ,  H01L21/82 ,  H01L27/092 ,  H01L27/112 ,  H01L27/118 ,  H03K19/0948 ,  H03K19/173 ,  H03K19/094

公开(公告)号：DE3478175D1

公开(公告)日：1989-06-15

申请号：DE3478175

申请日：1984-02-20

Applicant: IBM

Inventor： ELLIS WAYNE FREDERICK ,  GRIFFIN WILLIAM ROBERT ,  TROUTMAN RONALD ROY

IPC: H03K19/0948 ,  H03K17/06 ,  H03K17/687 ,  H03K19/017 ,  H03K5/02

Abstract: A driver or pull up circuit is provided which includes a pull up transistor (T5) of a given conductivity type and a precharged bootstrap capacitor (CB) which discharges fully through a second transistor (T3) having a conductivity type opposite to that of the pull up transistor to the control gate or electrode of the pull up transistor. A further transistor (T1) may be used to initiate discharge by providing power supply voltage to the control gate of the pull up transistor.

公开(公告)号：DE3471413D1

公开(公告)日：1988-06-23

申请号：DE3471413

申请日：1984-11-14

Applicant: IBM

Inventor： GRIFFIN WILLIAM ROBERT ,  HELLER LAWRENCE GRIFFITH

IPC: H03K19/0175 ,  H03K19/096 ,  H03K19/173

Abstract: A clocked differential cascode voltage switch (CVS) logic system is provided for a complete logic family which has a first switching circuit (10) that produces a given output signal at a first output node (14) and a second switching circuit (12) that produces a second output signal which is the complement of that of the given output signal at a second output node (18). First and second clocked devices (24, 28) are connected from the first and second output nodes (14, 18), respectively, to a voltage source (VH), the first and second inverters (32, 34) are connected to the first and second output nodes (14, 18), respectively. Additionally, a regenerative circuit (26, 30) may be connected between the first and second output nodes (14, 18) and the voltage source (VH).