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    PROCESS FOR PRODUCING A HIGH-DENSITY INTEGRATED READ-ONLY MEMORY
    1.
    发明专利
    PROCESS FOR PRODUCING A HIGH-DENSITY INTEGRATED READ-ONLY MEMORY 未知

    公开(公告)号：DE3071648D1

    公开(公告)日：1986-07-24

    申请号：DE3071648

    申请日：1980-07-24

    Applicant: IBM

    Inventor： FORTINO ANDREAS GUILLERMO ,  GEIPEL HENRY JOHN JR ,  HELLER LAWRENCE GRIFFITH ,  SILVERMAN RONALD

    IPC: H01L21/822 ,  G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/225 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/112 ,  H01L29/08 ,  H01L29/78

    Abstract: A method of making a transistor array includes forming a plurality of gate electrodes insulated from a semiconductor substrate having an impurity of a given conductivity, introducing a first impurity having a conductivity opposite to that of the given conductivity into a given region of the substrate which is adjacent to an edge of each of the gate electrodes, introducing a second impurity having the given conductivity into given regions adjacent to selected gate electrodes, the second impurity having a significantly higher diffusivity than that of the first impurity in the semiconductor substrate, and driving the second impurity along the surface of the semiconductor substrate to form in the substrate under each of the selected gate electrodes a region having a concentration of impurity of the given conductivity higher than that of the semiconductor substrate. The transistor array may be used, e.g. to make a read only memory (ROM) by connecting appropriate current sensing means to each of the given regions to indicate the presence or absence of the higher diffusivity impurity when a predetermined voltage is applied to the gate electrodes. In one embodiment, the semiconductor substrate is made of P type conductivity, the first impurity is arsenic which produces N type conductivity regions and the second impurity is boron, which produces P type conductivity. Since boron has a higher diffusivity than arsenic, after they are driven by heating the boron impurity produces a high threshold region under the gate electrode when introduced in sufficiently high concentration.

    7.
    发明专利
    未知

    公开(公告)号：DE2707967A1

    公开(公告)日：1977-10-06

    申请号：DE2707967

    申请日：1977-02-24

    Applicant: IBM

    Inventor： HELLER LAWRENCE GRIFFITH ,  TERMAN LEWIS MADISON

    IPC: H03M1/44 ,  G11C11/56 ,  G11C19/18 ,  G11C19/36 ,  G11C27/02 ,  H03K4/02 ,  H03M1/00 ,  H03M1/66 ,  H03K13/03 ,  H03K3/53 ,  G06F5/00 ,  G06F1/02

    Abstract: A bucket brigade circuit is described for generating a sequence of packets of charge carriers of the form QR/2, QR/4, QR/8....QR/2N where N is an integer. The charge packets thus generated can be employed in combinations in either digital-to-analog or analog-to-digital converters. The charge generation circuit requires two equal capacitors which are used for charge redistribution. To obtain accurate quantities of charge in the generated charge packets the capacitors employed should be large, however the use of large capacitors results in low operating speed because of the large charge transfer time constants involved. The described circuit provides a scheme to reduce charge transfer time constants and therefore obtain greater speed while still permitting the use of large capacitors for high accuracy. The circuit includes a small coupling capacitor connected in series with one of the charge redistribution capacitors to produce a total capacitance which is equal to or smaller than the coupling capacitance. The sequence of charge carriers produced by the circuit can be injected into either a bucket brigade circuit or a charge-coupled-device circuit for use, for example, in digital-to-analog and analog-to-digital converters.

    8.
    发明专利
    未知

    公开(公告)号：DE2708636A1

    公开(公告)日：1977-09-08

    申请号：DE2708636

    申请日：1977-02-28

    Applicant: IBM

    Inventor： HELLER LAWRENCE GRIFFITH ,  TERMAN LEWIS MADISON

    IPC: H03M1/44 ,  H01L29/768 ,  H01L29/78 ,  H03M1/00 ,  H03K13/03 ,  H03K3/53 ,  H03K3/78 ,  G06F5/00 ,  G06F1/04

    Abstract: Analog-to-digital (A/D) and digital-to-analog (D/A) converter circuits are provided using charge redistribution. The analog-to-digital converter circuit also employs successive approximation binary search techniques wherein the number of search voltages generated is a minimum. The analog-to-digital circuit includes a digital-to-analog converter circuit, a comparator circuit and a logic control means. The digital-to-analog circuit, under control of the logic means, accepts a reference voltage input and produces a sequence of search voltages which are compared with an unknown analog input voltage at the comparator. The resultant outputs from the comparator are applied to the control logic to determine the search voltage sequence. The digital-to-analog converter for the aforesaid circuit is provided in one embodiment employing charge-coupled-device technology. A substrate and two storage electrodes are combined to produce two potential storage wells and a transfer electrode is provided to move charge carriers between the storage wells. A reference charge packet QR is stored and divided by charge redistribution between the two potential wells to produce a sequence of charge packets of value QR/2, QR/4, QR/8, QR/16 etc. which can be selectively combined to produce analog output of a D/A converter. In the A/D converter the same sequence of charge packets is used to generate the equivalent of a binary search sequence QR/2, QR/2+/-QR/4, QR/2+/-QR/4+/-QR/8 etc. In another embodiment a bucket brigade device is provided to accomplish the same result. Because of the technique of charge redistribution wherein precise amounts of charge can be shifted in either direction between storage means, the total number of search value steps is a minimum.

    9.
    发明专利
    未知

    公开(公告)号：DE2644593A1

    公开(公告)日：1977-04-28

    申请号：DE2644593

    申请日：1976-10-02

    Applicant: IBM

    Inventor： HELLER LAWRENCE GRIFFITH

    IPC: H01L29/762 ,  G11C19/28 ,  H01L21/339 ,  H01L27/10 ,  H01L29/768 ,  H01L29/66

    Abstract: A method and apparatus for duplicating or replicating an original packet of charge carriers such as electrons or holes while leaving the original charge packet unchanged and still available for further processing is described. A charge-coupled device (CCD) circuit is provided using gate displacement charge flow in combination with a bucket brigade circuit. The CCD circuit includes a first +CCD well, a source diffusion and a second CCD well. An original charge packet is introduced into the first CCD well, the gate of which being precharged to a given source potential. The charge packet in the first CCD well reduces the magnitude of the source potential and it is immediately restored by current flow which in turn causes charge carriers to transfer from the source diffusion into the second CCD well until a charge packet is contained in the second CCD well which is a replica of the original charge packet.

    10.
    发明专利
    未知

    公开(公告)号：IT1150032B

    公开(公告)日：1986-12-10

    申请号：IT2368880

    申请日：1980-07-25

    Applicant: IBM

    Inventor： FORTINO ANDRES GUILLERMO ,  GEIPEL HENRY JOHN JR ,  HELLER LAWRENCE GRIFFITH ,  SILVERMAN RONALD

    IPC: H01L21/822 ,  G11C11/56 ,  G11C17/00 ,  G11C17/12 ,  H01L21/225 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/04 ,  H01L27/10 ,  H01L27/112 ,  H01L29/08 ,  H01L29/78 ,  H01C

    Abstract: A method of making a transistor array includes forming a plurality of gate electrodes insulated from a semiconductor substrate having an impurity of a given conductivity, introducing a first impurity having a conductivity opposite to that of the given conductivity into a given region of the substrate which is adjacent to an edge of each of the gate electrodes, introducing a second impurity having the given conductivity into given regions adjacent to selected gate electrodes, the second impurity having a significantly higher diffusivity than that of the first impurity in the semiconductor substrate, and driving the second impurity along the surface of the semiconductor substrate to form in the substrate under each of the selected gate electrodes a region having a concentration of impurity of the given conductivity higher than that of the semiconductor substrate. The transistor array may be used, e.g. to make a read only memory (ROM) by connecting appropriate current sensing means to each of the given regions to indicate the presence or absence of the higher diffusivity impurity when a predetermined voltage is applied to the gate electrodes. In one embodiment, the semiconductor substrate is made of P type conductivity, the first impurity is arsenic which produces N type conductivity regions and the second impurity is boron, which produces P type conductivity. Since boron has a higher diffusivity than arsenic, after they are driven by heating the boron impurity produces a high threshold region under the gate electrode when introduced in sufficiently high concentration.

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