公开(公告)号：DE3885408T2

公开(公告)日：1994-05-11

申请号：DE3885408

申请日：1988-08-18

Applicant: IBM

Inventor： BASS ROY S ,  BHATTACHARYYA ARUP ,  GRISE GARY D

IPC: H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/10 ,  G11C17/00

Abstract: A non-volatile memory cell comprising a field effect transistor having source, gate, and drain electrodes (60, 40, 65). The gate structure (50) includes a gate stack having a dielectric layer (20), a charge storage structure (30) comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means (35, 25). A control electrode (40) is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.

公开(公告)号：DE3885408D1

公开(公告)日：1993-12-09

申请号：DE3885408

申请日：1988-08-18

Applicant: IBM

Inventor： BASS ROY S ,  BHATTACHARYYA ARUP ,  GRISE GARY D

IPC: H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/10 ,  G11C17/00

Abstract: A non-volatile memory cell comprising a field effect transistor having source, gate, and drain electrodes (60, 40, 65). The gate structure (50) includes a gate stack having a dielectric layer (20), a charge storage structure (30) comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means (35, 25). A control electrode (40) is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.