公开(公告)号：JPH10335465A

公开(公告)日：1998-12-18

申请号：JP11651698

申请日：1998-04-27

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  GEFFKEN ROBERT M ,  LAM CHUNG H ,  LEIDY ROBERT K

IPC: H01L21/82 ,  H01L23/525

Abstract: PROBLEM TO BE SOLVED: To provide an antifuse structure and method for personalizing a semiconductor device which can overcome the limitations of the prior art. SOLUTION: An antifuse 100 of the preferred embodiment comprises a two layer transformble insulator core between two electrodes 102, 104. The transformable insulator core is normally non-conductive but can be transformed into a conductive material by supplying a sufficient voltage across the electrodes 102, 104. The two layer core preferably comprises an injector layer 106 and a dielectric layer 108. The injector layer 106 preferably comprises a two phase material such as silicon rich nitride or silicon rich oxide. Initially, the injector layer 106 and the dielectric layer 108 are non-conductive. When a sufficient voltage is applied, the core fuses together and becomes conductive.

公开(公告)号：FR2346855A1

公开(公告)日：1977-10-28

申请号：FR7703516

申请日：1977-02-01

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  SILVERMAN RONALD

IPC: H01L21/033 ,  H01L27/10 ,  H01L21/316 ,  H01L21/321 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/04

Abstract: This describes a process for fabricating transistor memory cell arrays which includes forming a thin oxide which is continuous over the entire area and which is continuously protected from the time it is deposited so that subsequent processing steps will not cause any change in the thickness of the thin oxide except where deliberately desired. By first depositing a protective masking film and subsequently removing this film in a series of steps, so that this film is lost in the fabrication process, the need for using the dual dielectric insulating layers required in the prior art can be eliminated. By eliminating such dual dielectric insulating layers the performance and density of the arrays can be improved.

公开(公告)号：DE3885408D1

公开(公告)日：1993-12-09

申请号：DE3885408

申请日：1988-08-18

Applicant: IBM

Inventor： BASS ROY S ,  BHATTACHARYYA ARUP ,  GRISE GARY D

IPC: H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/10 ,  G11C17/00

Abstract: A non-volatile memory cell comprising a field effect transistor having source, gate, and drain electrodes (60, 40, 65). The gate structure (50) includes a gate stack having a dielectric layer (20), a charge storage structure (30) comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means (35, 25). A control electrode (40) is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.

公开(公告)号：DE3175263D1

公开(公告)日：1986-10-09

申请号：DE3175263

申请日：1981-06-25

Applicant: IBM

Inventor： BASIRE DOMINIQUE ,  BHATTACHARYYA ARUP ,  HOWARD JAMES ,  MOLLIER PIERRE

IPC: G11C17/00 ,  G11C17/08 ,  G11C17/16 ,  H01L23/525

Abstract: An electrically programmable read only memory assembly having cells arranged at the intersections of bit lines (BL1) and word lines (WL1, WL2), wherein each cell is formed of a bipolar transistor provided with a base region (70) and an emitter region (71) covered with a dielectric layer (2) made of an oxide or titanate of a transition metal. The cell in this condition represents a binary 0 information bit. The application of an appropriate voltage of approximately 4 volts to the pads of this cell through its corresponding bit line (BL1) and word line (WL2) causes the dielectric layer to break down and places the bit line in ohmic contact with the emitter, which sets the cell in its second condition representing a binary "1" information bit.

公开(公告)号：CA1159918A

公开(公告)日：1984-01-03

申请号：CA358899

申请日：1980-08-25

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  CHU WEI-KAN ,  HOWARD JAMES K ,  WIEDMAN FRANCIS W

IPC: H01G4/33 ,  H01G4/10 ,  H01G4/08

Abstract: ULTRA-THIN FILM CAPACITOR AND METHOD FOR MANUFACTURE THEREOF A suitable substrate is provided to which is applied a metal electrically conductive film electrode. The substrate and electrically conductive electrode film are then exposed to ion beam implantation of O+ or N+ ions to impregnate the surface of the metal electrode with O+ or N+ ions. Thereafter, the substrate and electrically conductive film having implanted O+ or N+ ions is annealed so as to stabilize the oxide structure which has been implanted into the surface of the electrically conductive film to provide an ultra-thin dielectric film. FI 9-79-058

公开(公告)号：DE3474247D1

公开(公告)日：1988-10-27

申请号：DE3474247

申请日：1984-06-08

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  WEN HO CHUNG

IPC: H05K3/46 ,  H01L21/48 ,  H01L23/08 ,  H05K3/40

Abstract: A first level interconnection structure is fabricated by forming conductor patterns (11) on the top surface of a thin flexible polymer film (10) temporarily supported on a rigid thin ceramic or metal support member (6) having windows (14) therein. Via openings (18) in the bottom surface of the polymer film are made to selected conductors (11), and the openings are filled with bonding metallurgy (20). The lower surface of the film is coated with a partially cured polymide adhesive (16). The adhesive (16) is removed in the via areas to expose the bonding metallurgy (20). This first layer structure is electrically tested and then transferred to the ceramic substrate of a VSLI circuit interconnection module on which corresponding metal pads are formed for pad-to-pad contact. When pressure and heat are applied, there occurs simultaneous bonding of the metal pads on the substrate and of the film directly to the substrate. A second level interconnection structure is formed in the same manner and bonded to the top surface of the first level structure. Additional level structures may be similarly superimposed to form a multilayer interconnection structure. During bonding, the lamination of the layers occurs in such a way that a single solid film is formed with the inductors embedded therein. One or more integrated circuit chips may then be bonded by their contact pads to the conductors on the upper most level interconnection structure.

公开(公告)号：DE3068441D1

公开(公告)日：1984-08-09

申请号：DE3068441

申请日：1980-09-15

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  CHU WEI-KAN ,  HOWARD JAMES KENT ,  WIEDMANN FRANCIS WALTER

IPC: H01G4/33 ,  H01G4/10

公开(公告)号：FR2316740A1

公开(公告)日：1977-01-28

申请号：FR7615011

申请日：1976-05-13

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  JOSHI MADHUKAR L ,  KROLL CHARLES T ,  SILVERMAN RONALD

IPC: H01L27/112 ,  G11C17/00 ,  G11C17/08 ,  H01L21/3105 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/088 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/04 ,  H01L21/72 ,  G11C11/40

Abstract: Fully integrated non-volatile and fixed threshold field effect devices are fabricated in N-channel technology on a single semiconductor substrate. MOSFET devices of the metal-nitride-oxide-semiconductor (MNOS) devices are used both as fixed threshold support devices and as variable threshold non-volatile memory array devices. Extremely stable and reproducible device characteristics result from the use of low charge containing dielectrics which allow optimum variable threshold stability and allow the use of operating potentials compatable with conventional fixed threshold FET devices. Low temperature processing following deposition of variable threshold gate dielectric enables all enhancement mode operation. A field oxide structure including a thin silicon dioxide layer, an aluminum oxide layer and a nitride layer provides parasitic threshold voltages in excess of 60 volts and prevents sub-threshold leakage.

公开(公告)号：DE3885408T2

公开(公告)日：1994-05-11

申请号：DE3885408

申请日：1988-08-18

Applicant: IBM

Inventor： BASS ROY S ,  BHATTACHARYYA ARUP ,  GRISE GARY D

IPC: H01L21/8247 ,  G11C16/04 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78 ,  H01L27/10 ,  G11C17/00

Abstract: A non-volatile memory cell comprising a field effect transistor having source, gate, and drain electrodes (60, 40, 65). The gate structure (50) includes a gate stack having a dielectric layer (20), a charge storage structure (30) comprising a layer of silicon-rich silicon nitride having sufficient excess silicon to provide appreciable charge storage enhancement, without providing appreciable charge conductance enhancement, as compared to stoichiometric silicon nitride, and a charge injection means (35, 25). A control electrode (40) is disposed on the gate stack for effecting charge transfer to and from the silicon-rich silicon nitride layer through the charge injection means. An array of these cells is formed by disposing the FETs within independently biased substrate portions. Thus the cells can be overwritten without an intervening erasure cycle.

公开(公告)号：DE2860591D1

公开(公告)日：1981-04-23

申请号：DE2860591

申请日：1978-12-01

Applicant: IBM

Inventor： BHATTACHARYYA ARUP ,  WIEDMAN III FRANCIS WALTER

IPC: H01L29/73 ,  G11C11/404 ,  H01L21/225 ,  H01L21/285 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8229 ,  H01L27/07 ,  H01L27/102 ,  H01L21/70

Abstract: A semiconductor structure, formed within a recessed oxide isolation region, includes a semiconductor substrate of a first conductivity type within which a collector of opposite conductivity type is formed below the surface of the substrate and extending in part to the surface of the substrate for ease of contact. A first layer of doped polycrystalline silicon or polysilicon is formed on a first portion of the surface of the substrate and in electrical contact with the substrate which acts as the base of a transistor. The first polysilicon layer is oxidized to form an outer insulating layer thereover. A second doped polysilicon layer is disposed over the outer insulating layer onto a second portion of the surface of the substrate so as to be spaced from the first portion by only the thickness of the outer insulating layer on the first polysilicon layer. The dopant in the second polysilicon layer is driven into the surface of the semiconductor substrate to form an emitter therein. Means, which may include a portion of the second polysilicon layer, are provided for electrically contacting the collector to thus form a completed compact bipolar transistor which has very high performance.