公开(公告)号：SG100759A1

公开(公告)日：2003-12-26

申请号：SG200105944

申请日：2001-09-19

Applicant: IBM

Inventor： H BERNHARD POGGE ,  CHANDRIKA PRASAD ,  ROY YU

IPC: H01L21/68 ,  H01L21/98 ,  H01L23/538

Abstract: A semiconductor device structure including fine-pitch connections between chips is fabricated using stud/via matching structures. The stud and via are aligned and connected, thereby permitting fine-pitch chip placement and electrical interconnections. A chip support is then attached to the device. A temporary chip alignment structure includes a transparent plate exposed to ablating radiation; the plate is then detached and removed. This method permits interconnection of multiple chips (generally with different sizes, architectures and functions) at close proximity and with very high wiring density. The device may include passive components located on separate chips, so that the device includes chips with and without active devices.