公开(公告)号：JP2000003308A

公开(公告)日：2000-01-07

申请号：JP9622899

申请日：1999-04-02

Applicant: IBM

Inventor： DHONG SANG H ,  HALM PETER HOFSTAY ,  MELTZER DAVID ,  JOEL ABRAHAM SILVERMAN

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for realizing simultaneous, namely overlapped access to plural cache levels to reduce the waiting time of penalty of an upper level cache mistake. SOLUTION: The demand of a value (data or an instruction) is issued by a process 104 and is transferred to a lower level cache before it is decided whether a cache mistake of the value is generated at a cache of an upper level. In an execution configuration in which a lower level is an L2 cache, it is possible to directly supply a processor with a value. An address decoder operates at the upper level cache in parallel and can satisfy plural simultaneous memory demands. One of addresses (selected by order of priority logic on the basis of hit-miss information from the upper level cache) is gated to a work line driver of a memory array of the cache at the lower level by a multiplexer. Several bits among the address which do not need conversion from virtual into real can be immediately decoded.