公开(公告)号：JPH11282675A

公开(公告)日：1999-10-15

申请号：JP6999

申请日：1999-01-04

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレイション

Inventor： JEFFREY L BURNS ,  DHONG SANG H ,  KEVIN JOHN NOUKA ,  JOEL ABRAHAM SILVERMAN

IPC: G06F9/38 ,  G06F7/48 ,  G06F9/302 ,  G06F9/305 ,  G06F9/32

CPC classification number: G06F9/3001 ,  G06F7/48 ,  G06F9/30094

Abstract: PROBLEM TO BE SOLVED: To improve the data processing efficiency by deciding the small, large and equal condition code bits concerning an instruction via an execution unit in parallel to execution of an arithmetic operation.
SOLUTION: A BPU 18 includes a counter register CRT 40, a link register LR 42 and a condition register CR 44, and the value of the BPU 18 can be used to solve a condition branch instruction. The CR 44 (and a CR rename buffer 46) has several different fields including one or more bits respectively. These fields contain the condition codes shown according to their value which are smaller or larger than or equal to zero. The condition branch instruction that cannot be solved before its execution by referring to the CR 44, LR 42 or CRT 40 can be estimated by using preferably a normal branch circuit, e.g. a branch history table or a branch target address cache which is included in the PB 18.
COPYRIGHT: (C)1999,JPO

Abstract translation: 要解决的问题：通过与执行算术运算并行地执行与执行单元相关的指令的小，大和相等条件码位来提高数据处理效率。 解决方案：BPU18包括计数器寄存器CRT40，链接寄存器LR42和条件寄存器CR44，并且可以使用BPU 18的值来求解条件转移指令。 CR 44（和CR重命名缓冲器46）分别具有包括一个或多个位的几个不同的字段。 这些字段包含根据其值小于或等于零的值显示的条件代码。 通过参考CR 44，LR 42或CRT 40在其执行之前无法解决的条件分支指令可以通过使用优选的正常分支电路来估计。 分支历史表或分支目标地址缓存，其包括在PB 18中。

公开(公告)号：JP2005045221A

公开(公告)日：2005-02-17

申请号：JP2004180883

申请日：2004-06-18

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BUCKI ROBERT JOHN ,  DHONG SANG HOO ,  JOEL ABRAHAM SILVERMAN ,  OSAMU TAKAHASHI

IPC: H01L21/82 ,  G06F17/50 ,  H03K19/00 ,  H03K19/177

CPC classification number: G06F17/5054

Abstract: PROBLEM TO BE SOLVED: To shorten a signal delay and lower a power consumption by customizing a wire-segment length in a programmable logic array so that a parasitic capacitance related to an interconnection line is minimized.
SOLUTION: A first array composed of a junction leaf cell is constituted so that tiles are arranged by using at least one 1-cell and at least one 0-cell, and at least one logical expression is defined by the relative positional relationship of mutual cells configuring the array. The interconnection lines in which lengths are optimized are added to the array. Each interconnection line in which the lengths are optimized is ended by the leaf cell in the array, with which the interconnection lines are brought into contact lastly. The leaf cell can be used as a floating leaf cell. In the floating leaf cell, a pair of any junction leaf cells are electrically insulated mutually until the interconnection lines in which the lengths are optimized are added to the constitution.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过定制可编程逻辑阵列中的线段长度来缩短信号延迟并降低功耗，使得与互连线相关的寄生电容最小化。 解决方案：由结叶单元组成的第一阵列被构造成使得通过使用至少一个1单元和至少一个0单元布置瓦片，并且至少一个逻辑表达式由相对位置关系 的相互单元配置阵列。 将长度优化的互连线添加到阵列中。 长度优化的每个互连线由阵列中的叶单元结束，最后互连线与之接触。 叶细胞可以用作浮叶细胞。 在浮动叶细胞中，一对任何连接叶细胞相互电绝缘，直到将长度优化的互连线添加到构造中。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JPH11353177A

公开(公告)日：1999-12-24

申请号：JP11974499

申请日：1999-04-27

Applicant: IBM

Inventor： SAN HOO ZON ,  HAAM PETER HOFSTY ,  KEVIN JOHN NOFUKA ,  JOEL ABRAHAM SILVERMAN

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To use the register set in a processor more efficiently by mapping sources and target architecture registers in instructions to one group of physical registers and generating a list of tags corresponding to physical registers which are not used here. SOLUTION: One given instruction is loaded to one execution unit and the list of tags corresponding to specific registers which are not used is generated. All the items in a table A for the physical registers are linked on logical OR basis to generate a vector for accurately discriminating which register is used by an instruction being executed. This vector is passed to a structure B which generates the tag of a physical register possibly assigned as a target to a following target although it is not used. The vector structure B generates a bit indicating the adequacy of the generated tag as well. The generated tag becomes ineffective only when the number of usable physical registers is insufficient.

公开(公告)号：JP2000003308A

公开(公告)日：2000-01-07

申请号：JP9622899

申请日：1999-04-02

Applicant: IBM

Inventor： DHONG SANG H ,  HALM PETER HOFSTAY ,  MELTZER DAVID ,  JOEL ABRAHAM SILVERMAN

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide a method for realizing simultaneous, namely overlapped access to plural cache levels to reduce the waiting time of penalty of an upper level cache mistake. SOLUTION: The demand of a value (data or an instruction) is issued by a process 104 and is transferred to a lower level cache before it is decided whether a cache mistake of the value is generated at a cache of an upper level. In an execution configuration in which a lower level is an L2 cache, it is possible to directly supply a processor with a value. An address decoder operates at the upper level cache in parallel and can satisfy plural simultaneous memory demands. One of addresses (selected by order of priority logic on the basis of hit-miss information from the upper level cache) is gated to a work line driver of a memory array of the cache at the lower level by a multiplexer. Several bits among the address which do not need conversion from virtual into real can be immediately decoded.

公开(公告)号：JPH11345168A

公开(公告)日：1999-12-14

申请号：JP9647799

申请日：1999-04-02

Applicant: IBM

Inventor： SAN HOO ZON ,  JOEL ABRAHAM SILVERMAN

IPC: G06F12/08 ,  G06F12/10

Abstract: PROBLEM TO BE SOLVED: To provide a method for accessing a cache memory in a data processing system. SOLUTION: This cache memory is provided with a transformation index buffer 33, together with a memory array 31 and a directory. The cache memory can be accessed by an effective address containing a byte field, row field and effective page number field. In order to facilitate a cache access process, a transformation array 34 having the same number of rows as the transformation index buffer 33 is provided. The respective rows of the transformation array 34 have as many array items as the product of a row number per page of a system memory and the set associativity of a cache. The transformation array 34 is updated after the contents of the directory or transformation index buffer 33 have been updated. In order to decide whether or not the cache memory stores data related to the translated address, the transformation array can be accessed corresponding to the contents of the row field at the effective address.

公开(公告)号：JPH10207691A

公开(公告)日：1998-08-07

申请号：JP148598

申请日：1998-01-07

Applicant: IBM

Inventor： NAOAKI AOKI ,  OSAMU TAKAHASHI ,  JOEL ABRAHAM SILVERMAN ,  SAN FU DON

IPC: G06F7/38 ,  G06F7/50 ,  G06F7/505 ,  G06F7/508

Abstract: PROBLEM TO BE SOLVED: To actualize high performance with a small area by implementing logical NOR a bit line pair and a sense amplifier and generating a NOR output, connecting exclusive OR gates to corresponding NOR outputs and one specific true input signal, and generating an increased output signal. SOLUTION: Referring to an output signal B63, an input signal A63 represents the least significant digit bit, so a column B63 should execute an inverted function. The column B63 does not have 1 cell 66, so the output of a sense amplifier 72 is always 1. This a output is then exclusively ORed with an input signal A63. When the input signal A63 is 1 in binary notation, the value of the output signal B63 is 0 in binary notation and when 0, the outputs signal is 1. Referring to an output signal B62, a column B62 includes one cell, which is connected to a word line 64 corresponding to the complementary of A63, the output of an amplifier 72 is the complementary of the complementary or 63, and this is 63 true. This output is exclusively ORed with the input signal A62 and B62 is generated.