公开(公告)号：CA2663966A1

公开(公告)日：2010-01-24

申请号：CA2663966

申请日：2009-04-23

Applicant: IBM

Inventor： DOUSKEY STEVEN MICHAEL ,  HAMILTON MICHAEL JOHN ,  SCHENCK BRANDON EDWARD

IPC: G01R31/319

Abstract: An adaptation of a test data register (TDR) structure defined by the IEEE 1149.1 Joint Tag Action Group (JTAG) interface standard to provide a debugging path. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, the present apparatus is for extending the IEEE 1149.1 JTAG standard to provide an asynchronous protocol for bypassing test circuitry and bi-directionally communicating with functional circuitry. The apparatus includes an integrated circuit having function register and JTAG standard TDR. Digital logic is configured to control the direct transfer of data between the JTAG standard TDR and the function register.

公开(公告)号：CA2663971A1

公开(公告)日：2010-01-24

申请号：CA2663971

申请日：2009-04-23

Applicant: IBM

Inventor： DOUSKEY STEVEN MICHAEL ,  HAMILTON MICHAEL JOHN ,  SCHENCK BRANDON EDWARD

IPC: G06F13/42 ,  G01R31/3181

Abstract: An adaptation of standard boundary cell architecture defined by the IEEE 1149.1 Joint Test Action Group (JTAG) interface standard to provide paths to functional circuitry via the re-use of JTAG standard test data registers (TDR) and interface. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, an integrated circuit is provided with a plurality of function registers along with a plurality of I/O units. The I/O units are arranged in a serial communications chain located around the boundary of the integrated circuit's functional circuitry. Each of the I/O units include JTAG standard serial TDR in serial communication with adjacent I/O units. Moreover, each I/O unit includes JTAG standard parallel TDR that is associated with and in parallel communication with the I/O unit's JTAG standard serial TDR. Further still, a digital logic interface is configured to control the direct transfer of data between the JTAG standard parallel TDR and a corresponding one of the plurality of function registers. As a result of the re-use of existing boundary scan architecture, a significant reduction in wiring congestion is realized. Thus, asynchronous communication is provided without sacrificing valuable integrated circuit real estate.