公开(公告)号：DE69012954T2

公开(公告)日：1995-04-06

申请号：DE69012954

申请日：1990-10-09

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  DOUSKEY STEVEN MICHAEL ,  MEYER JEROME MARTIN

IPC: G01R31/28 ,  G01R31/00 ,  G06F11/16 ,  G06F11/22 ,  G06F11/267 ,  G01R31/3177

Abstract: A method and apparatus for identifying stuck faults in an oscillator used for providing a oscillator input signal (12) to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system and testing technique. A pair of shift register latches (SRLs) (20,30) are provided in the integrated circuit chip having a logical one signal applied to a data input of the SRLs. The oscillator input signal is applied to a data clock input of a first one (20) of the SRLs and an inverted oscillator input signal is applied to the data clock input of a second one (30) of the SRLs. Then the scan data output (SDO) of the test SRLs is detected responsive to the applied oscillator and inverted oscillator input signals to identify a stuck fault.

公开(公告)号：CA2663971A1

公开(公告)日：2010-01-24

申请号：CA2663971

申请日：2009-04-23

Applicant: IBM

Inventor： DOUSKEY STEVEN MICHAEL ,  HAMILTON MICHAEL JOHN ,  SCHENCK BRANDON EDWARD

IPC: G06F13/42 ,  G01R31/3181

Abstract: An adaptation of standard boundary cell architecture defined by the IEEE 1149.1 Joint Test Action Group (JTAG) interface standard to provide paths to functional circuitry via the re-use of JTAG standard test data registers (TDR) and interface. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, an integrated circuit is provided with a plurality of function registers along with a plurality of I/O units. The I/O units are arranged in a serial communications chain located around the boundary of the integrated circuit's functional circuitry. Each of the I/O units include JTAG standard serial TDR in serial communication with adjacent I/O units. Moreover, each I/O unit includes JTAG standard parallel TDR that is associated with and in parallel communication with the I/O unit's JTAG standard serial TDR. Further still, a digital logic interface is configured to control the direct transfer of data between the JTAG standard parallel TDR and a corresponding one of the plurality of function registers. As a result of the re-use of existing boundary scan architecture, a significant reduction in wiring congestion is realized. Thus, asynchronous communication is provided without sacrificing valuable integrated circuit real estate.

公开(公告)号：DE102021128930A1

公开(公告)日：2022-06-09

申请号：DE102021128930

申请日：2021-11-08

Applicant: IBM

Inventor： DOUSKEY STEVEN MICHAEL ,  FORLENZA ORAZIO PASQUALE ,  KUSKO MARY P ,  MOTIKA FRANCO ,  SALEM GERARD MICHAEL

IPC: G01R31/3187

Abstract: Ein Verfahren umfasst ein Ausführen eines Tests an einer ersten Struktur und einer zweiten Struktur einer eingebauten Selbsttestschaltung. Sowohl die erste wie die zweite Struktur enthalten eine Mehrzahl von Flipflops, die als eine Mehrzahl von Blockketten angeordnet sind. Das Verfahren umfasst auch ein Entladen eines ersten Ergebnisses des Tests von der Mehrzahl von Blockketten der ersten Struktur und eines zweiten Ergebnisses des Tests von der Mehrzahl von Blockketten der zweiten Struktur. Das Verfahren umfasst ferner auf Grundlage einer fehlenden Übereinstimmung des ersten Ergebnisses mit dem zweiten Ergebnis ein Ermitteln, dass die Mehrzahl von Blockketten der ersten Struktur ein fehlerhaftes Flipflop enthält.

公开(公告)号：CA2663966A1

公开(公告)日：2010-01-24

申请号：CA2663966

申请日：2009-04-23

Applicant: IBM

Inventor： DOUSKEY STEVEN MICHAEL ,  HAMILTON MICHAEL JOHN ,  SCHENCK BRANDON EDWARD

IPC: G01R31/319

Abstract: An adaptation of a test data register (TDR) structure defined by the IEEE 1149.1 Joint Tag Action Group (JTAG) interface standard to provide a debugging path. Existing multi-core processor solutions are covered, but an expansion for a more generic solution is provided. In general, the present apparatus is for extending the IEEE 1149.1 JTAG standard to provide an asynchronous protocol for bypassing test circuitry and bi-directionally communicating with functional circuitry. The apparatus includes an integrated circuit having function register and JTAG standard TDR. Digital logic is configured to control the direct transfer of data between the JTAG standard TDR and the function register.

公开(公告)号：DE69012954D1

公开(公告)日：1994-11-03

申请号：DE69012954

申请日：1990-10-09

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  DOUSKEY STEVEN MICHAEL ,  MEYER JEROME MARTIN

IPC: G01R31/28 ,  G01R31/00 ,  G06F11/16 ,  G06F11/22 ,  G06F11/267 ,  G01R31/318

Abstract: A method and apparatus for identifying stuck faults in an oscillator used for providing a oscillator input signal (12) to an integrated circuit chip of the type conforming to a Level Sensitive Scan Design (LSSD) system and testing technique. A pair of shift register latches (SRLs) (20,30) are provided in the integrated circuit chip having a logical one signal applied to a data input of the SRLs. The oscillator input signal is applied to a data clock input of a first one (20) of the SRLs and an inverted oscillator input signal is applied to the data clock input of a second one (30) of the SRLs. Then the scan data output (SDO) of the test SRLs is detected responsive to the applied oscillator and inverted oscillator input signals to identify a stuck fault.