Fft processor with unique addressing
    1.
    发明授权
    Fft processor with unique addressing 失效
    FFT处理器具有独特的寻址功能

    公开(公告)号:US3673399A

    公开(公告)日:1972-06-27

    申请号:US3673399D

    申请日:1970-05-28

    Applicant: IBM

    CPC classification number: G06F17/142

    Abstract: A real time digital Fourier analyzer using the Cooley-Tukey algorithm for calculating the Fast Fourier Transform. An arithmetic unit simultaneously performs the two complex calculations Ar Br + Wr Cr and A(r n/2) Br - Wr Cr. The calculated results are simultaneously stored and retrieved in an in-place operation in dual buffers in successive iterations. Addressing of the buffers uses a single binary address counter and sequential bit complementing for simultaneously addressing both buffers. Parity checking of the binary counter output address controls multiplexing logic to selectively address the buffers to store the calculated results into the desired buffer storage locations.

    Abstract translation: 一种使用Cooley-Tukey算法计算快速傅立叶变换的实时数字傅里叶分析仪。 算术单元同时执行两个复数计算Ar = Br + Wr Cr和A(r + n / 2)= Br-Wr Cr。 计算结果在连续迭代中以双缓冲器的就地操作同时存储和检索。 缓冲器的寻址使用单个二进制地址计数器和顺序位补码来同时寻址两个缓冲区。 二进制计数器输出地址的奇偶校验控制多路复用逻辑以选择性地寻址缓冲器以将计算出的结果存储到期望的缓冲存储位置。

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