公开(公告)号：DE60113780D1

公开(公告)日：2005-11-10

申请号：DE60113780

申请日：2001-07-11

Applicant: IBM

Inventor： HANNA STEPHEN DALE

IPC: G06F11/25 ,  G01R31/317 ,  G01R31/3185

Abstract: A method and apparatus for tracing hardware states using dynamically reconfigurable test circuits (35) provides improved debug and troubleshooting capability for functional logic implemented within field programmable logic arrays (FPGAs) (33). Special test logic configurations (49) may be loaded to enhance the debugging of a system using FPGAs (33). Registers are used to capture snapshots of internal signals (50, 51, 52) for access by a trace program and a test multiplexer is used to provide real-time output to test pins for use with external test equipment. By retrieving the hardware snapshot information with a trace program running on a system in which the FPGA is used, software and hardware debugging are coordinated, providing a sophisticated model of overall system behaviour. Special test circuits (49) are implemented within the test logic configurations to enable detection of various events and errors. Counters (48) are used to capture count values when system processor execution reaches a hardware trace point or when events occur. Comparators (45) are used to detect specific data or address values and event detectors (47) are used to detect particular logic value combinations that occur within the functional logic.

公开(公告)号：CA2354248A1

公开(公告)日：2002-02-02

申请号：CA2354248

申请日：2001-07-27

Applicant: IBM

Inventor： HANNA STEPHEN DALE

IPC: G06F11/25 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/30 ,  G06F9/44

Abstract: A method and apparatus for tracing hardware states using dynamically reconfigurable test circuits provides improved debug and troubleshooting capability for function al logic implemented within field programmable logic arrays (FPGAs). Special test logic configurations may be loaded to enhance the debugging of a system using FPGAs. Registers are used to capture snapshots of internal signals for access by a trace program and a test multiplexer is use d to provide real-time output to test pins for use with external test equipment. By retrieving the hardware snapshot information with a trace program running on a system in which the FPGA is used, software and hardware debugging are coordinated, providing a sophisticated model of overa ll system behavior. Special test circuits are implemented within the test logic configurations t o enable detection of various events and errors. Counters are used to capture count values when system processor execution reaches a hardware trace point or when events occur. Comparators a re used to detect specific data or address values and event detectors are used to detect particular logic value combinations that occur within the functional logic.

公开(公告)号：CA2051177C

公开(公告)日：1996-05-14

申请号：CA2051177

申请日：1991-09-11

Applicant: IBM

Inventor： FISCHER LISA LYN ,  HANNA STEPHEN DALE

IPC: G06F13/28 ,  G06F13/30 ,  G06F13/362 ,  G06F13/368 ,  G06F12/00 ,  G06F13/16

Abstract: Bus master for use in computer system includes logic for determining the number of words remaining to be transferred in a DMA operation to supply signals to permit arbitration to start for the next DMA request, thereby avoiding an idle cycle. A timeout state machine is also included to prevent the bus master state machine from hanging in a state with no exit. Errors can be masked to permit analysis of system problems.

公开(公告)号：DE3786526T2

公开(公告)日：1994-02-17

申请号：DE3786526

申请日：1987-10-02

Applicant: IBM

Inventor： DOMINQUES RUBEN ,  LOPEZ JESUS CABRERA ,  FINLAY DAVID ERNEST ,  STEVENSON DAVID CRAIG ,  HANNA STEPHEN DALE ,  ZEGAFUSE DONALD WARD

IPC: G06K15/00 ,  B41J2/485 ,  G06F3/12 ,  G06K15/02 ,  G09G1/14 ,  G09G5/22 ,  G06K15/12

Abstract: A character generator with multidirectional scan and variable line and character (or symbol) size capability is disclosed. Universality is implemented by producing a serial binary stream which can be used to print or display in any of eight combinations of scan direction and progression, that is, for scan direction left to right, or vice versa, progressing up or down, or scan direction top to bottom or vice versa, progressing left or right. In formatting the serial binary stream, a font is accessed (for basic symbol definition), which selectively provides for orthogonal scans of the symbol definitions. Variable line size is implemented by terminating a symbol row (or line) based on a predetermined size criteria regardless of the comparable font dimension and "filling" up to the line size to the extent the corresponding font dimension is less than the predetermined size criteria. Variable character (or symbol) size is implemented by independently multiplying the effect of a symbol definition by selected (integral) factors, in orthogonal directions. The general architecture includes a font table (for symbol definition), an address/escape (A/E) table, defining symbol size for comparison with line size parameters, a character position escape (CPE) table to define a leading character or symbol on each line and a page buffer (PB) memory defining the characters (symbols) in the document and their relationship with other characters (symbols). Access to the CPE table allows access to the PB, from there to the A/E table and from there to the font allows extraction of selected and appropriate portions of the symbol definition to make up the binary system.

公开(公告)号：DE60113780T2

公开(公告)日：2006-06-22

申请号：DE60113780

申请日：2001-07-11

Applicant: IBM

Inventor： HANNA STEPHEN DALE

IPC: G01R31/3185 ,  G06F11/25 ,  G01R31/317

Abstract: A method and apparatus for tracing hardware states using dynamically reconfigurable test circuits (35) provides improved debug and troubleshooting capability for functional logic implemented within field programmable logic arrays (FPGAs) (33). Special test logic configurations (49) may be loaded to enhance the debugging of a system using FPGAs (33). Registers are used to capture snapshots of internal signals (50, 51, 52) for access by a trace program and a test multiplexer is used to provide real-time output to test pins for use with external test equipment. By retrieving the hardware snapshot information with a trace program running on a system in which the FPGA is used, software and hardware debugging are coordinated, providing a sophisticated model of overall system behaviour. Special test circuits (49) are implemented within the test logic configurations to enable detection of various events and errors. Counters (48) are used to capture count values when system processor execution reaches a hardware trace point or when events occur. Comparators (45) are used to detect specific data or address values and event detectors (47) are used to detect particular logic value combinations that occur within the functional logic.

公开(公告)号：AT306084T

公开(公告)日：2005-10-15

申请号：AT01305974

申请日：2001-07-11

Applicant: IBM

Inventor： HANNA STEPHEN DALE

IPC: G06F11/25 ,  G01R31/317 ,  G01R31/3185

Abstract: A method and apparatus for tracing hardware states using dynamically reconfigurable test circuits (35) provides improved debug and troubleshooting capability for functional logic implemented within field programmable logic arrays (FPGAs) (33). Special test logic configurations (49) may be loaded to enhance the debugging of a system using FPGAs (33). Registers are used to capture snapshots of internal signals (50, 51, 52) for access by a trace program and a test multiplexer is used to provide real-time output to test pins for use with external test equipment. By retrieving the hardware snapshot information with a trace program running on a system in which the FPGA is used, software and hardware debugging are coordinated, providing a sophisticated model of overall system behaviour. Special test circuits (49) are implemented within the test logic configurations to enable detection of various events and errors. Counters (48) are used to capture count values when system processor execution reaches a hardware trace point or when events occur. Comparators (45) are used to detect specific data or address values and event detectors (47) are used to detect particular logic value combinations that occur within the functional logic.

公开(公告)号：GB2368421A

公开(公告)日：2002-05-01

申请号：GB0110357

申请日：2001-04-27

Applicant: IBM

Inventor： HANNA STEPHEN DALE

IPC: G06F11/25 ,  G01R31/317 ,  G01R31/3185 ,  G06F11/267 ,  G06F11/27

Abstract: A method and apparatus for tracing hardware states using dynamically reconfigurable test circuits (35) provides improved debug and troubleshooting capability for functional logic implemented within field programmable logic arrays (FPGAs) (33). Special test logic configurations may be loaded to enhance the debugging of a system using FPGAs (33). Registers are used to capture snapshots of internal signals for access by a trace program and a test multiplexer is used to provide real-time output to test pins for use with external test equipment. By retrieving the hardware snapshot information with a trace program running on a system in which the FPGA is used, software and hardware debugging are coordinated, providing a sophisticated model of overall system behaviour. Special test circuits are implemented within the test logic configurations to enable detection of various events and errors. Counters are used to capture count values when system processor execution reaches a hardware trace point or when events occur. Comparators are used to detect specific data or address values and event detectors are used to detect particular logic value combinations that occur within the functional logic.

公开(公告)号：DE3787073T2

公开(公告)日：1994-03-17

申请号：DE3787073

申请日：1987-10-02

Applicant: IBM

Inventor： FINLAY DAVID ERNEST ,  HANNA STEPHEN DALE ,  STEVENSON DAVID CRAIG ,  VARGA JOHN THOMAS

IPC: G06K15/00 ,  B41J2/485 ,  B41J5/30 ,  G06F3/12 ,  G06K15/02 ,  G09G5/24 ,  G06K15/12

Abstract: A character generator with multidirectional scan and variable line and character (or symbol) size capability is disclosed. Universality is implemented by producing a serial binary stream which can be used to print or display in any of eight combinations of scan direction and progression, that is, for scan direction left to right, or vice versa, progressing up or down, or scan direction top to bottom or vice versa, progressing left or right. In formatting the serial binary stream, a font is accessed (for basic symbol definition), which selectively provides for orthogonal scans of the symbol definitions. Variable line size is implemented by terminating a symbol row (or line) based on a predetermined size criteria regardless of the comparable font dimension and "filling" up to the line size to the extent the corresponding font dimension is less than the predetermined size criteria. Variable character (or symbol) size is implemented by independently multiplying the effect of a symbol definition by selected (integral) factors, in orthogonal directions. The general architecture includes a font table (for symbol definition), an address/escape (A/E) table, defining symbol size for comparison with line size parameters, a character position escape (CPE) table to define a leading character or symbol on each line and a page buffer (PB) memory defining the characters (symbols) in the document and their relationship with other characters (symbols). Access to the CPE table allows access to the PB, from there to the A/E table and from there to the font allows extraction of selected and appropriate portions of the symbol definition to make up the binary system.

公开(公告)号：DE3786526D1

公开(公告)日：1993-08-19

申请号：DE3786526

申请日：1987-10-02

Applicant: IBM

Inventor： DOMINQUES RUBEN ,  LOPEZ JESUS CABRERA ,  FINLAY DAVID ERNEST ,  STEVENSON DAVID CRAIG ,  HANNA STEPHEN DALE ,  ZEGAFUSE DONALD WARD

IPC: G06K15/00 ,  B41J2/485 ,  G06F3/12 ,  G06K15/02 ,  G09G1/14 ,  G09G5/22 ,  G06K15/12

Abstract: A character generator with multidirectional scan and variable line and character (or symbol) size capability is disclosed. Universality is implemented by producing a serial binary stream which can be used to print or display in any of eight combinations of scan direction and progression, that is, for scan direction left to right, or vice versa, progressing up or down, or scan direction top to bottom or vice versa, progressing left or right. In formatting the serial binary stream, a font is accessed (for basic symbol definition), which selectively provides for orthogonal scans of the symbol definitions. Variable line size is implemented by terminating a symbol row (or line) based on a predetermined size criteria regardless of the comparable font dimension and "filling" up to the line size to the extent the corresponding font dimension is less than the predetermined size criteria. Variable character (or symbol) size is implemented by independently multiplying the effect of a symbol definition by selected (integral) factors, in orthogonal directions. The general architecture includes a font table (for symbol definition), an address/escape (A/E) table, defining symbol size for comparison with line size parameters, a character position escape (CPE) table to define a leading character or symbol on each line and a page buffer (PB) memory defining the characters (symbols) in the document and their relationship with other characters (symbols). Access to the CPE table allows access to the PB, from there to the A/E table and from there to the font allows extraction of selected and appropriate portions of the symbol definition to make up the binary system.

公开(公告)号：CA2354248C

公开(公告)日：2006-09-19

申请号：CA2354248

申请日：2001-07-27

Applicant: IBM

Inventor： HANNA STEPHEN DALE

IPC: G06F11/25 ,  G06F11/30 ,  G01R31/317 ,  G01R31/3185 ,  G06F9/44

Abstract: A method and apparatus for tracing hardware states using dynamically reconfigurable test circuits provides improved debug and troubleshooting capability for function al logic implemented within field programmable logic arrays (FPGAs). Special test logic configurations may be loaded to enhance the debugging of a system using FPGAs. Registers are used to capture snapshots of internal signals for access by a trace program and a test multiplexer is use d to provide real-time output to test pins for use with external test equipment. By retrieving the hardware snapshot information with a trace program running on a system in which the FPGA is used, software and hardware debugging are coordinated, providing a sophisticated model of overa ll system behavior. Special test circuits are implemented within the test logic configurations t o enable detection of various events and errors. Counters are used to capture count values when system processor execution reaches a hardware trace point or when events occur. Comparators a re used to detect specific data or address values and event detectors are used to detect particular logic value combinations that occur within the functional logic.