公开(公告)号：US3898630A

公开(公告)日：1975-08-05

申请号：US40561773

申请日：1973-10-11

Applicant: IBM

Inventor： HANSEN AAGE A ,  LANE RALPH D

IPC: G11C17/00 ,  G11C11/34 ,  G11C16/06 ,  G11C16/10 ,  G11C16/26 ,  G11C11/40

CPC classification number: G11C16/26 ,  G11C16/10

Abstract: Disclosed is a high voltage driver circuit for writing information into a read mostly memory array, the memory cells of the array being characterized by requiring much higher potential levels for writing information than for reading information.

公开(公告)号：US3893085A

公开(公告)日：1975-07-01

申请号：US41958773

申请日：1973-11-28

Applicant: IBM

Inventor： HANSEN AAGE A

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/07 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC classification number: G11C16/0433 ,  H01L27/0716 ,  H01L29/7886

Abstract: Disclosed is a memory cell incorporating the major advantages of a read only storage (ROS) and having the flexibility of on-chip personalization after processing. In a memory matrix having orthogonally arranged bit lines and word lines with memory cells located at the cross points, each of the disclosed memory cells constructed in accordance with BIFET technology includes a floating gate avalanche breakdown MOS transistor (FAMOS) coupled to a bipolar transistor. The residual charge on the floating gate FAMOS transistor determines the logical state of the read mostly memory cell.

Abstract translation: 公开了一种结合了只读存储（ROS）的主要优点并且具有处理后片上个性化的灵活性的存储单元。 在具有正交布置的位线和具有位于交叉点处的存储器单元的字线的存储器矩阵中，根据BIFET技术构造的所公开的存储单元中的每一个包括耦合到双极晶体管的浮动栅极雪崩击穿MOS晶体管（FAMOS）。 浮栅FAMOS晶体管上的剩余电荷决定了大部分读存储单元的逻辑状态。

公开(公告)号：DE2455484A1

公开(公告)日：1975-06-05

申请号：DE2455484

申请日：1974-11-23

Applicant: IBM

Inventor： HANSEN AAGE A

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/07 ,  H01L29/788 ,  H01L29/792 ,  H01L27/10

Abstract: Disclosed is a memory cell incorporating the major advantages of a read only storage (ROS) and having the flexibility of on-chip personalization after processing. In a memory matrix having orthogonally arranged bit lines and word lines with memory cells located at the cross points, each of the disclosed memory cells constructed in accordance with BIFET technology includes a floating gate avalanche breakdown MOS transistor (FAMOS) coupled to a bipolar transistor. The residual charge on the floating gate FAMOS transistor determines the logical state of the read mostly memory cell.

公开(公告)号：DE2359153A1

公开(公告)日：1974-07-11

申请号：DE2359153

申请日：1973-11-28

Applicant: IBM

Inventor： HANSEN AAGE A ,  LANE RALPH D

IPC: G11C11/41 ,  G11C11/34 ,  G11C11/413 ,  G11C16/06 ,  G11C16/08 ,  G11C17/00 ,  G11C7/00

Abstract: A high-voltage integrated driver circuit for driving the word lines of a digital computer memory array of floating-gate avalanche-injection transistor memory cells, and for other applications where a high driving voltage is required. The disclosed driver circuit comprises a field-effect output transistor having a source electrode connected to a respective word line, a drain electrode adapted to have a chip select pulse signal applied thereto, and a gate electrode connected to selectably operable circuitry which may be conditioned either to a first state for clamping the voltage of the gate to cut off the output transistor and thereby maintain the output and the word line at a first voltage level, or to a second state for unclamping the voltage of the gate of the output transistor to permit the voltage of the output and the respective word line to swing with a high amplitude so as to cause the selected memory cell transistor to go into avalanche breakdown and thereby charge its floating gate so as to store a bit of information in the selected cell.

公开(公告)号：CA1048647A

公开(公告)日：1979-02-13

申请号：CA211475

申请日：1974-10-16

Applicant: IBM

Inventor： HANSEN AAGE A

IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/07 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

Abstract: READ MOSTLY MEMORY CELL HAVING BIPOLAR AND FAMOS TRANSISTOR Disclosed is a memory cell incorporating the major advantages of a read only storage (ROS) and having the flexibility of on-chip personalization after processing. In a memory matrix having orthogonally arranged bit lines and word lines with memory cells located at the cross points, each of the disclosed memory cells constructed in accordance with BIFET technology includes a floating gate avalanche breakdown MOS transistor(FAMOS) coupled to a bipolar transistor. The residual charge on the floating gate FAMOS transistor determines the logical state of the read mostly memory cell.