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    Complementary FET pulse level converter
    1.
    发明授权
    Complementary FET pulse level converter 失效
    互补FET脉冲电平转换器

    公开(公告)号：US3906254A

    公开(公告)日：1975-09-16

    申请号：US49494674

    申请日：1974-08-05

    Applicant: IBM

    Inventor： LANE RALPH D ,  MANNING RICHARD A

    IPC: H03K19/0185 ,  H03K19/08 ,  H03K3/353 ,  H03K17/60

    CPC classification number: H03K19/018521

    Abstract: An interfacing circuit for restoring voltage pulses to a desired fixed level. The circuit is particularly adapted to CMOS technology and includes features which result in rapid output rise and fall times, latching of the output voltage level, and isolation of the input following transition of the input voltage between its respective final levels. The circuit is also relatively insensitive to noise since it requires voltage transitions greater than the FET threshold levels to fully activate and switch the latching circuit means.

    Abstract translation: 一种用于将电压脉冲恢复到所需固定电平的接口电路。 该电路特别适用于CMOS技术，并且包括导致快速输出上升和下降时间，输出电压电平锁存以及输入电压在各自的最终电平转换之后的隔离的特征。 该电路对噪声也相对不敏感，因为它需要大于FET阈值电平的电压转换，以完全启动和切换锁存电路装置。

    ELECTRICALLY ERASABLE FLOATING GATE FET MEMORY CELL
    3.
    发明专利
    ELECTRICALLY ERASABLE FLOATING GATE FET MEMORY CELL 未知

    公开(公告)号：CA1023859A

    公开(公告)日：1978-01-03

    申请号：CA194527

    申请日：1974-03-08

    Applicant: IBM

    Inventor： ABBAS SHAKIR A ,  BARILE CONRAD A ,  LANE RALPH D ,  LIU PETER T

    IPC: G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L29/417 ,  H01L29/788 ,  H01L29/792 ,  H01L29/40

    Abstract: A read-mostly memory cell is disclosed comprising a floating gate avalanche injection field effect transistor storage device equipped with an erasing electrode. The memory portion of the erasable storage devices comprises a P channel FET having a floating polycrystalline silicon gate separated from an N-doped substrate by a layer of silicon dioxide. The erasing portion of the device comprises an erasing electrode separated from the polycrystalline silicon floating gate by a thermally grown layer of silicon dioxide having a leakage characteristic which is low in the presence of low electrical fields and high in the presence of high electrical fields. The floating gate is heavily doped with boron which also partially dopes the thermally grown silicon dioxide layer. The floating gate is charged negatively by avalanche breakdown of the FET drain while the erase gate is grounded to the substrate. The floating gate is discharged (erased) upon the application of a positive pulse to the erase electrode with respect to the semiconductor substrate causing electrodes on the charged floating gate to leak through the thermal oxide to the erasing electrode.

    4.
    发明专利
    未知

    公开(公告)号：DE2538453A1

    公开(公告)日：1976-04-01

    申请号：DE2538453

    申请日：1975-08-29

    Applicant: IBM

    Inventor： KNEPPER RONALD W ,  LANE RALPH D ,  LUDLOW PETER J ,  MOORE BARRY L

    IPC: H03K17/08 ,  H02H3/08 ,  H02H3/093 ,  H02H7/20 ,  H03K17/082 ,  H03K19/0185 ,  H02H7/12

    Abstract: An over current protect circuit for a common bus driver having a complementary pair FET output includes a pair of AND circuits responsive to the gate-source and drain-source voltages for charging separate time integrating capacitors. If a threshold charge is reached a latch is triggered, which in turn disables the driver via a NAND gate and Inverter, and discharges the active capacitor. The latch is reset by dropping the driver enable line. As an alternative, high driver current may be sensed by placing a resistor in series with each output FET and charging the associated capacitor in response to a high current through the resistor.

    8.
    发明专利
    未知

    公开(公告)号：FR2285737A1

    公开(公告)日：1976-04-16

    申请号：FR7525143

    申请日：1975-08-07

    Applicant: IBM

    Inventor： KNEPPER RONALD W ,  LANE RALPH D ,  LUDLOW PETER J ,  MOORE BARRY L

    IPC: H03K17/08 ,  H02H3/08 ,  H02H3/093 ,  H02H7/20 ,  H03K17/082 ,  H03K19/0185

    Abstract: An over current protect circuit for a common bus driver having a complementary pair FET output includes a pair of AND circuits responsive to the gate-source and drain-source voltages for charging separate time integrating capacitors. If a threshold charge is reached a latch is triggered, which in turn disables the driver via a NAND gate and Inverter, and discharges the active capacitor. The latch is reset by dropping the driver enable line. As an alternative, high driver current may be sensed by placing a resistor in series with each output FET and charging the associated capacitor in response to a high current through the resistor.

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