公开(公告)号：US3812336A

公开(公告)日：1974-05-21

申请号：US31616372

申请日：1972-12-18

Applicant: IBM

Inventor： HSIAO M ,  BOSSEN D ,  HAUGH C

IPC: G06F12/16 ,  G06F11/10 ,  G11C29/00 ,  H03M13/00 ,  G06F11/12

CPC classification number: G11C29/88

Abstract: This specification describes a scheme for swapping bits between words of a memory when a multiple error condition is detected in any word of the memory by a single error correction and multiple error detection system monitoring the memory. The swapping of the bits between the words is done in terms of orthogonal Latin squares insuring that no combination of any two bits is repeated in the reconfigured words. This insures that with a single swapping of the bits the detected multiple error condition is eliminated and makes it highly unlikely that another double error condition will be produced by the swapping.