公开(公告)号：US3825893A

公开(公告)日：1974-07-23

申请号：US36448073

申请日：1973-05-29

Applicant: IBM

Inventor： BOSSEN D ,  PATEL A ,  HONG S ,  HSIAO M

IPC: G06F12/16 ,  G06F11/10 ,  H03M13/00 ,  H03M13/19 ,  H04L1/10

CPC classification number: G06F11/1012 ,  H03M13/19

Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1''s and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.

公开(公告)号：US3812336A

公开(公告)日：1974-05-21

申请号：US31616372

申请日：1972-12-18

Applicant: IBM

Inventor： HSIAO M ,  BOSSEN D ,  HAUGH C

IPC: G06F12/16 ,  G06F11/10 ,  G11C29/00 ,  H03M13/00 ,  G06F11/12

CPC classification number: G11C29/88

Abstract: This specification describes a scheme for swapping bits between words of a memory when a multiple error condition is detected in any word of the memory by a single error correction and multiple error detection system monitoring the memory. The swapping of the bits between the words is done in terms of orthogonal Latin squares insuring that no combination of any two bits is repeated in the reconfigured words. This insures that with a single swapping of the bits the detected multiple error condition is eliminated and makes it highly unlikely that another double error condition will be produced by the swapping.

公开(公告)号：CA932467A

公开(公告)日：1973-08-21

申请号：CA103625

申请日：1971-01-25

Applicant: IBM

Inventor： HSIAO M

IPC: H03M13/19

公开(公告)号：BR7404579D0

公开(公告)日：1975-01-07

申请号：BR457974

申请日：1974-06-04

Applicant: IBM

Inventor： BOSSEN D ,  HSIAO M ,  PATEL A

IPC: G06F12/16 ,  G06F11/10 ,  G11B20/18 ,  H03M13/00 ,  G11C13/00 ,  G11C9/00

Abstract: 1440285 Error correction INTERNATIONAL BUSINESS MACHINES CORP 24 April 1974 [4 June 1973] 18002/74 Heading G4A Data is stored on a plurality of independently accessible storage units, e.g. magnetic tape cartridges, and check bits, each of which is a function of a corresponding bit from each data storage unit, are stored on a check unit which may be used, in the event of a catastrophic loss of data on one of the data storage units and detected by an error checking facility associated with that unit, to restore the data on that unit. Extension of the system to include more than one check unit, each of which stores the check bits for one position of a Hamming code, is also mentioned. In normal operation, one of the data storage units is selected and data thereon is updated by read before write heads 15, 21. The difference e jk between each old bit and the corresponding new bit is EXORed with the corresponding old parity bit p k from the check unit to update the parity bits. The parity bits are initially recorded by successively (or simultaneously) reading the data storage units to record the modulo 2 sums of the corresponding bits, and data restoration is similar reading from the good data storage units and the check unit.