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公开(公告)号：DE602005010773D1
公开(公告)日：2008-12-18
申请号：DE602005010773
申请日：2005-03-14
Applicant: IBM
Inventor： GABILLARD BERTRAND , HAUVILLER PHILIPPE , MALTERE ALEXANDRE , RO CHRISTOPHER
Abstract: There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.
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公开(公告)号：DE60213443T2
公开(公告)日：2007-08-23
申请号：DE60213443
申请日：2002-10-10
Applicant: IBM
Inventor： HAUVILLER PHILIPPE , VALLET VINCENT
Abstract: There is disclosed a transition detection, validation and memorization (TDVM) circuit that detects the position of a transition in a stream of serially transmitted binary data (bits) that are over sampled and generates a control signal indicating which sampled signal represents the best the data. The incoming data stream is over sampled by the n phases of a multiple phase clock signal. The frequency of the multiphase clock signal is the same or half of the frequency of the incoming data for stability reasons. The n over sampled signals (S) are fed in the TDVM circuit which is comprised of three sections. The first section detects the transition at the positions of two consecutive sampled signals according to a specific signal processing which requires to perform twice, three comparisons on six consecutive over sampled signals (the central one being excluded at each time). The second section validates the second detection as the transition position. The third section memorizes the validated transition position and generates a control signal that is used to recover the data. For instance, this control signal can be used in a sample selection/data alignment circuit to select the over sampled signal that is the best suited for subsequent processing
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公开(公告)号：AT413757T
公开(公告)日：2008-11-15
申请号：AT05101950
申请日：2005-03-14
Applicant: IBM
Inventor： GABILLARD BERTRAND , HAUVILLER PHILIPPE , MALTERE ALEXANDRE , RO CHRISTOPHER
Abstract: There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.
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公开(公告)号：AT334523T
公开(公告)日：2006-08-15
申请号：AT02783062
申请日：2002-10-10
Applicant: IBM
Inventor： HAUVILLER PHILIPPE , VALLET VINCENT
Abstract: There is disclosed a transition detection, validation and memorization (TDVM) circuit that detects the position of a transition in a stream of serially transmitted binary data (bits) that are over sampled and generates a control signal indicating which sampled signal represents the best the data. The incoming data stream is over sampled by the n phases of a multiple phase clock signal. The frequency of the multiphase clock signal is the same or half of the frequency of the incoming data for stability reasons. The n over sampled signals (S) are fed in the TDVM circuit which is comprised of three sections. The first section detects the transition at the positions of two consecutive sampled signals according to a specific signal processing which requires to perform twice, three comparisons on six consecutive over sampled signals (the central one being excluded at each time). The second section validates the second detection as the transition position. The third section memorizes the validated transition position and generates a control signal that is used to recover the data. For instance, this control signal can be used in a sample selection/data alignment circuit to select the over sampled signal that is the best suited for subsequent processing
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Patent Agency Ranking
公开(公告)号：GB2526796A
公开(公告)日：2015-12-09
申请号：GB201409758
申请日：2014-06-02
Applicant: IBM
Inventor： RIVIER MICHEL , GABILLARD BERTRAND , HAUVILLER PHILIPPE , ELLIS-MONAGHAN JOHN JOSEPH
IPC: G06F17/50
Abstract: A method of checking layout integrity comprises the steps of receiving inputs defining a plurality of devices for a layout, generating a signature for each device in the layout, when created, from one or more parameters of the device, storing the generated signatures with the layout, receiving the stored layout and signatures, regenerating each signature for each device in the stored layout, and comparing each regenerated signature with the corresponding stored signature. The signature comprises the sum of coordinates, perimeter and area of the devices.
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公开(公告)号：DE602004019041D1
公开(公告)日：2009-03-05
申请号：DE602004019041
申请日：2004-11-03
Applicant: IBM
Inventor： VALLET VINCENT , HAUVILLER PHILIPPE
Abstract: An improved data recovery circuit based on an oversampling technique wherein intersymbol interference (ISI) is compensated. A detection circuit is connected at the output of a conventional recovery circuit. The recovered data is applied to the detection circuit which includes flip-flops to memorize the previous state of the recovered data when no data transition is detected within a predefined number of clock periods. The detection circuit detects sequences of a predetermined number of consecutive identical bits which indicates the presence of ISI. It generates a feedback signal that is applied to the decision circuit and to the data sample selection circuit to shift the selection of a data sample of one position to compensate ISI.
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公开(公告)号：AT421202T
公开(公告)日：2009-01-15
申请号：AT04105474
申请日：2004-11-03
Applicant: IBM
Inventor： VALLET VINCENT , HAUVILLER PHILIPPE
Abstract: An improved data recovery circuit based on an oversampling technique wherein intersymbol interference (ISI) is compensated. A detection circuit is connected at the output of a conventional recovery circuit. The recovered data is applied to the detection circuit which includes flip-flops to memorize the previous state of the recovered data when no data transition is detected within a predefined number of clock periods. The detection circuit detects sequences of a predetermined number of consecutive identical bits which indicates the presence of ISI. It generates a feedback signal that is applied to the decision circuit and to the data sample selection circuit to shift the selection of a data sample of one position to compensate ISI.
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公开(公告)号：DE60213443D1
公开(公告)日：2006-09-07
申请号：DE60213443
申请日：2002-10-10
Applicant: IBM
Inventor： HAUVILLER PHILIPPE , VALLET VINCENT
Abstract: There is disclosed a transition detection, validation and memorization (TDVM) circuit that detects the position of a transition in a stream of serially transmitted binary data (bits) that are over sampled and generates a control signal indicating which sampled signal represents the best the data. The incoming data stream is over sampled by the n phases of a multiple phase clock signal. The frequency of the multiphase clock signal is the same or half of the frequency of the incoming data for stability reasons. The n over sampled signals (S) are fed in the TDVM circuit which is comprised of three sections. The first section detects the transition at the positions of two consecutive sampled signals according to a specific signal processing which requires to perform twice, three comparisons on six consecutive over sampled signals (the central one being excluded at each time). The second section validates the second detection as the transition position. The third section memorizes the validated transition position and generates a control signal that is used to recover the data. For instance, this control signal can be used in a sample selection/data alignment circuit to select the over sampled signal that is the best suited for subsequent processing
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公开(公告)号：DE3781277D1
公开(公告)日：1992-09-24
申请号：DE3781277
申请日：1987-10-09
Applicant: IBM
Inventor： HAUVILLER PHILIPPE , VERHAEGHE MICHEL
Abstract: To extend the conversion capability of the DAC from four-bits to seven bits, each switch of a first set of switches (10,12) is connected between a respective top of the first string (R1-R16) of resistors and the converter output. Each switch of a second set of switches (14) is connected between the second top of a resistive element of the first string and a second mode (M7) of a second resistor string consisting of 2(power 3)- 2 i.e. six, resistive elements (Z1-Z6). An OR gate (22) and a further switch (SW21) are responsive to a specific combination A2,A1,A0 equals one of the three extension bits A0,A1,A2, to disconnect the second string from the first and second modes (M1,M7).
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