公开(公告)号：AT413757T

公开(公告)日：2008-11-15

申请号：AT05101950

申请日：2005-03-14

Applicant: IBM

Inventor： GABILLARD BERTRAND ,  HAUVILLER PHILIPPE ,  MALTERE ALEXANDRE ,  RO CHRISTOPHER

IPC: H04L25/02 ,  G11C27/02 ,  H03F1/02 ,  H03F3/45 ,  H04L25/06

Abstract: There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.

公开(公告)号：AU2003250884A1

公开(公告)日：2004-02-23

申请号：AU2003250884

申请日：2003-06-13

Applicant: IBM

Inventor： GABILLARD BERTRAND ,  GIRARD PHILIPPE ,  RIVIER MICHEL ,  VOISIN FABRICE

IPC: H03F3/343

Abstract: There is disclosed an improved 2-stage large bandwidth amplifier (20) comprised of two stages formed by first and second bipolar transistors (Q1,Q2) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (Vin) is applied to the base of said first transistor via an input terminal (11), while the output signal (Vout) is available at an output terminal (12) connected to the collector of said second transistor. A parallel feedback structure (13') is provided. It consists, in a first branch, of two diodes (D1,D2) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q3) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage. The resistor is connected to the common node of said first and second transistors to inject the feedback signal (Vf). Because, the two bodies have a low internal resistance and reduce the collector capacitance of the second transistor, the overall bandwidth of the improved amplifier is significantly extended in the very high frequencies (e.g. 20 GHz and above).

公开(公告)号：DE60303046D1

公开(公告)日：2006-02-02

申请号：DE60303046

申请日：2003-06-13

Applicant: IBM

Inventor： GABILLARD BERTRAND ,  GIRARD PHILIPPE ,  RIVIER MICHEL ,  VOISIN FABRICE

IPC: H03F3/343

Abstract: There is disclosed an improved 2-stage large bandwidth amplifier (20) comprised of two stages formed by first and second bipolar transistors (Q1,Q2) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (Vin) is applied to the base of said first transistor via an input terminal (11), while the output signal (Vout) is available at an output terminal (12) connected to the collector of said second transistor. A parallel feedback structure (13') is provided. It consists, in a first branch, of two diodes (D1,D2) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q3) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage. The resistor is connected to the common node of said first and second transistors to inject the feedback signal (Vf). Because, the two bodies have a low internal resistance and reduce the collector capacitance of the second transistor, the overall bandwidth of the improved amplifier is significantly extended in the very high frequencies (e.g. 20 GHz and above).

公开(公告)号：DE69122491D1

公开(公告)日：1996-11-07

申请号：DE69122491

申请日：1991-02-28

Applicant: IBM

Inventor： GABILLARD BERTRAND ,  GIRARD PHILLIPE ,  GRANDGUILLOT MICHEL

IPC: H03K3/356 ,  H03K19/00 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/0944

Abstract: Input ECL level signals are received and converted into output CMOS level signals by an improved high-speed, low power consumption input buffer (30). The input buffer (30) biased between first and second supply voltage (Vcc, Vee) is comprised of three stages. The first stage (11A) consists of a conventional emitter-follower transistor (Q1) and a current-switch (13) connected in series as standard. The input signal VIN at the ECL level is applied to the base of the emitter-follower transistor (Q1). The output signals (VA, VB) obtained therefrom drive a second stage which consists of a level-shifter circuit (20), which supplies two pairs of output signals (V1, V2; V1', V2') for each phase. Each pair of output signals drives an output driver (31; 31') forming the third stage. The level-shifter circuit (20) is composed of two NPN bipolar transistor (T1; T2) connected in an emitter-follower configuration forming two branches. In each branch, the emitter load consists of three FET devices: two PFETs (P1, P3; P2, P4) and one NFET (N1; N2) serially connected. The common node (E; F) between the PFETs in one branch, is cross-coupled to the gate electrode of the NFET (N2; N1) of the other branch. The gate electrode of the PFET (P1; P2) connected to the emitter of the bipolar transistor (T1; T2) in one branch is driven by the potential of the common node formed by the other PFET (P4; P3) and the NFET (N2; N1) in the other branch. The IN PHASE (VOUT) and OUT OF PHASE (VOUT) circuit output signals are available at the circuit output terminals (32; 32') of said output drivers (31; 31') at the CMOS levels.

公开(公告)号：DE602005010773D1

公开(公告)日：2008-12-18

申请号：DE602005010773

申请日：2005-03-14

Applicant: IBM

Inventor： GABILLARD BERTRAND ,  HAUVILLER PHILIPPE ,  MALTERE ALEXANDRE ,  RO CHRISTOPHER

IPC: H04L25/02 ,  G11C27/02 ,  H03F1/02 ,  H03F3/45 ,  H04L25/06

Abstract: There is described an improved receiver which first comprises an analog input amplifier a sample and hold differential circuit and two stages of differential comparators that are connected in series, wherein the first stage consists of two comparators and the second stage of one comparator. By properly activating the switches with signals generated by a dedicated control logic, the input differential signal is sampled in the sample and hold circuit to generate first and second differential signals. The first differential signal holds a first state and the second differential signal propagates the second state. As result, the signal output by the second comparator stage reflects the differential offset minus the offset compensation.

公开(公告)号：DE60303046T2

公开(公告)日：2006-07-27

申请号：DE60303046

申请日：2003-06-13

Applicant: IBM

Inventor： GABILLARD BERTRAND ,  GIRARD PHILIPPE ,  RIVIER MICHEL ,  VOISIN FABRICE

IPC: H03F3/343

Abstract: There is disclosed an improved 2-stage large bandwidth amplifier (20) comprised of two stages formed by first and second bipolar transistors (Q1,Q2) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (Vin) is applied to the base of said first transistor via an input terminal (11), while the output signal (Vout) is available at an output terminal (12) connected to the collector of said second transistor. A parallel feedback structure (13') is provided. It consists, in a first branch, of two diodes (D1,D2) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q3) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage. The resistor is connected to the common node of said first and second transistors to inject the feedback signal (Vf). Because, the two bodies have a low internal resistance and reduce the collector capacitance of the second transistor, the overall bandwidth of the improved amplifier is significantly extended in the very high frequencies (e.g. 20 GHz and above).

公开(公告)号：AT314753T

公开(公告)日：2006-01-15

申请号：AT03766121

申请日：2003-06-13

Applicant: IBM

Inventor： GABILLARD BERTRAND ,  GIRARD PHILIPPE RES DE LA DAUP ,  RIVIER MICHEL ,  VOISIN FABRICE

IPC: H03F3/343

Abstract: There is disclosed an improved 2-stage large bandwidth amplifier (20) comprised of two stages formed by first and second bipolar transistors (Q1,Q2) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (Vin) is applied to the base of said first transistor via an input terminal (11), while the output signal (Vout) is available at an output terminal (12) connected to the collector of said second transistor. A parallel feedback structure (13') is provided. It consists, in a first branch, of two diodes (D1,D2) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q3) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage. The resistor is connected to the common node of said first and second transistors to inject the feedback signal (Vf). Because, the two bodies have a low internal resistance and reduce the collector capacitance of the second transistor, the overall bandwidth of the improved amplifier is significantly extended in the very high frequencies (e.g. 20 GHz and above).

公开(公告)号：DE69731580T2

公开(公告)日：2005-11-24

申请号：DE69731580

申请日：1997-04-08

Applicant: IBM

Inventor： GABILLARD BERTRAND

IPC: G11C8/10 ,  G11C11/418 ,  G11C8/00

公开(公告)号：DE69731580D1

公开(公告)日：2004-12-23

申请号：DE69731580

申请日：1997-04-08

Applicant: IBM

Inventor： GABILLARD BERTRAND

IPC: G11C8/10 ,  G11C11/418 ,  G11C8/00

公开(公告)号：GB2526796A

公开(公告)日：2015-12-09

申请号：GB201409758

申请日：2014-06-02

Applicant: IBM

Inventor： RIVIER MICHEL ,  GABILLARD BERTRAND ,  HAUVILLER PHILIPPE ,  ELLIS-MONAGHAN JOHN JOSEPH

IPC: G06F17/50

Abstract: A method of checking layout integrity comprises the steps of receiving inputs defining a plurality of devices for a layout, generating a signature for each device in the layout, when created, from one or more parameters of the device, storing the generated signatures with the layout, receiving the stored layout and signatures, regenerating each signature for each device in the stored layout, and comparing each regenerated signature with the corresponding stored signature. The signature comprises the sum of coordinates, perimeter and area of the devices.