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公开(公告)号：DE2351791A1
公开(公告)日：1974-04-25
申请号：DE2351791
申请日：1973-10-16
Applicant: IBM
Inventor： HEALEY ROBERT ALBERT
IPC: G06F9/24 , G06F7/78 , G06F9/22 , G06F9/34 , G06F9/40 , G06F12/08 , G06F12/12 , G11C7/00 , G06F9/06 , G06F13/06
Abstract: A storage device (hereinafter referred to as a high speed stack) having an access speed compatible with that of its processor has operands and/or operators entered therein (a push operation) and removed therefrom (a pop operation) for processing in a last-in-first-out order. The number of entries stored in the stack at any moment can become very large due to the nesting of operators. Since it is not economically feasible to provide a large capacity high speed stack, overflow of the stack into a slower speed storage device (hereinafter called a low speed stack) is provided. "Roll out" of entries to the low speed stack and "roll in" of the entries back to the high speed stack is effected as the high speed stack becomes relatively full and empty. A backup register, which normally stores the last entry transferred to the low speed stack, permits delay of roll in, roll out operations until the last possible moment. When a new entry is to be stored into the high speed stack (hereinafter referred to as a push operation) and the stack is full, the new entry is put into the backup register, a selected number of entries are rolled out from the high speed stack to the low speed stack and the new entry is then transferred from the register to the high speed stack. Roll in is not initiated even when the high speed stack is empty since the next available entry in the slow speed stack is available in the backup register for fast access by the processor. Only after the entry in the backup register is accessed for processing, the high speed stack being empty, does roll in of entries from the low speed stack to the high speed stack begin. High speed stack top and bottom pointers and a slow speed stack pointer are incremented and decremented to address the stacks and to determine the full, empty states of the high speed stack. With the stack bottom movable, the number of entries left in high speed storage on a roll out (or the number of entries not filled with valid data on a roll in) can be controlled by the roll in and roll out routines. Thus the stack mechanism can be tuned to an optimum based on the program language being processed.
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公开(公告)号：DE2429067A1
公开(公告)日：1975-01-16
申请号：DE2429067
申请日：1974-06-18
Applicant: IBM
Inventor： HEALEY ROBERT ALBERT , SHIMP EVERETT MONTAGUE
Abstract: 1457330 Data processing INTERNATIONAL BUSINESS MACHINES CORP 16 May 1974 [26 June 1973] 21688/74 Heading G4A In a data processing system having a high speed, last in-first out stack store for storing operands and operators for a processor, and a lower speed store arranged to store overflow copies of the data in the stack, roll in and roll out operations between the store and the stack store merely transfer a copy of a set of stack entries between the two stores and do not delete the entries from the source store. The arrangement reduces the number of roll operations required since, when an entry is to be made into a full stack, a roll out operation is initiated and the new entry overwrites the oldest stack entry which still remains in the stack. Then if a series of entries have to be removed from the stack, a roll-in is not necessary since the old entries still remain in the stack. Similarly following a roll-in operation, which is initiated when an entry is to be removed from the stack which is empty, entries may be entered into the stack overwriting the rolled-in entries without a roll-out operation since the entries being overwritten still remain in the lower speed store. The Specification describes in some detail the procedures involved in tracking the contents of the stack, and in addressing the lower speed store to ensure that the correct stack copies are accessed (roll-in) and the stack contents are copied into the correct locations in the lower speed store (roll-out). To this end three pointers and three status bits are used.
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公开(公告)号：DE2712224A1
公开(公告)日：1977-10-13
申请号：DE2712224
申请日：1977-03-19
Applicant: IBM
Inventor： HEALEY ROBERT ALBERT , JEREMIAH THOMAS LEO
Abstract: Size exception detection hardware for use with a digital data processor arithmetic unit for providing high-speed detection of lost data which results from storing an arithmetic result in a destination which is smaller than one or both of the source operands. In response to data processing machine instructions, the arithmetic unit performs arithmetic operations on variable length operands and sends the arithmetic results to variable length destinations. The operand and destination lengths are specified by length fields in the machine instruction. The destination length is specified independently of at least one of the operand lengths and hence may be less than such operand length. The size exception detection hardware looks at both the output field of the arithmetic unit and the destination length field in the machine instruction and generates a size exception program interrupt signal when the part of the arithmetic unit output field located outside of the destination length contains significant data. The size exception interrupt is generated during the same machine control cycle during which the arithmetic unit performs the arithmetic operation which gives rise to the size exception.
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公开(公告)号：AU2390777A
公开(公告)日：1978-10-12
申请号：AU2390777
申请日：1977-04-04
Applicant: IBM
Inventor： HEALEY ROBERT ALBERT , JEREMIAH THOMAS LEO
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