公开(公告)号：US3916388A

公开(公告)日：1975-10-28

申请号：US47482574

申请日：1974-05-30

Applicant: IBM

Inventor： SHIMP EVERETT MONTAGUE ,  SLIZ NICHOLAS BERNARD

IPC: G06F9/312 ,  G06F9/315 ,  G06F12/04 ,  G06F15/00

CPC classification number: G06F9/30043 ,  G06F9/30032 ,  G06F9/3816 ,  G06F12/04

Abstract: An improved multibyte data shifting apparatus is disclosed for use in a microprogram controlled data processing system to efficiently shift a multibyte data field accessed from a structured memory where it was stored across the boundary between a first and second memory word, and to load the data field justified, into a processor register. The shifting apparatus is responsive to a first microprogram control word specifying the multibyte data field length, to shift a first plurality of bytes accessed from the first memory word and to load it into a processor register in a position shifted such that the total multibyte field to be accessed will be justified. The amount of shift is determined by a binary adder operating on the low order bits of the storage address and the field length data. The binary adder generates a carry output which indicates that the multibyte field accessed lies across a memory word boundary. The carry output is connected to a branching unit in the microprogram controller causing the controller to branch to a second microprogram control word. The shifting apparatus is then responsive to the second microprogram control word to shift a second plurality of bytes, as the remaining portion of the multibyte field, accessed from the second memory word and to load it justified in the processor register. The multibyte data field is thereby accessed and justified in no more than two control word cycles. Both read and store accessing is accommodated by the invention.

Abstract translation: 公开了一种改进的多字节数据移位装置，用于微程序控制的数据处理系统，以有效地移动从结构化存储器访问的多字节数据字段，其中它被存储在第一和第二存储器字之间的边界上，并且加载数据字段 有理由进入处理器寄存器。 换档装置响应于指定多字节数据字段长度的第一微程序控制字来移动从第一存储器字访问的第一多个字节，并将其加载到处理器寄存器中，使得总多字节字段 被访问是有道理的。 移位量由对存储地址和字段长度数据的低位进行操作的二进制加法器确定。 二进制加法器产生一个进位输出，指示所访问的多字节字段跨越一个存储器字边界。 进位输出连接到微程序控制器中的分支单元，使得控制器分支到第二微程序控制字。 移位装置然后响应于第二微程序控制字来移位第二多个字节，因为多字节字段的剩余部分从第二存储器字访问，并将其加载到处理器寄存器中。 因此，多字节数据字段被访问并且在不超过两个控制字周期内被对齐。 本发明容纳了读取和存储访问。

公开(公告)号：DE2429067A1

公开(公告)日：1975-01-16

申请号：DE2429067

申请日：1974-06-18

Applicant: IBM

Inventor： HEALEY ROBERT ALBERT ,  SHIMP EVERETT MONTAGUE

IPC: G06F9/34 ,  G06F9/40 ,  G06F12/00 ,  G06F12/08 ,  G11C7/00 ,  G06F13/06

Abstract: 1457330 Data processing INTERNATIONAL BUSINESS MACHINES CORP 16 May 1974 [26 June 1973] 21688/74 Heading G4A In a data processing system having a high speed, last in-first out stack store for storing operands and operators for a processor, and a lower speed store arranged to store overflow copies of the data in the stack, roll in and roll out operations between the store and the stack store merely transfer a copy of a set of stack entries between the two stores and do not delete the entries from the source store. The arrangement reduces the number of roll operations required since, when an entry is to be made into a full stack, a roll out operation is initiated and the new entry overwrites the oldest stack entry which still remains in the stack. Then if a series of entries have to be removed from the stack, a roll-in is not necessary since the old entries still remain in the stack. Similarly following a roll-in operation, which is initiated when an entry is to be removed from the stack which is empty, entries may be entered into the stack overwriting the rolled-in entries without a roll-out operation since the entries being overwritten still remain in the lower speed store. The Specification describes in some detail the procedures involved in tracking the contents of the stack, and in addressing the lower speed store to ensure that the correct stack copies are accessed (roll-in) and the stack contents are copied into the correct locations in the lower speed store (roll-out). To this end three pointers and three status bits are used.

公开(公告)号：DE2626432A1

公开(公告)日：1977-01-13

申请号：DE2626432

申请日：1976-06-12

Applicant: IBM

Inventor： GOODING DAVID NORMAN ,  SHIMP EVERETT MONTAGUE

IPC: G06F7/48 ,  G06F7/493 ,  G06F7/494 ,  G06F7/50 ,  G06F7/508 ,  G06F5/00

Abstract: 1512476 Arithmetic units INTERNATIONAL BUSINESS MACHINES CORP 6 May 1976 [17 June 1975] 18555/76 Heading G4A An arithmetic unit capable of operating on operands in zoned or packed BCD format as well as binary comprises an adder 20 having input modifying circuitry 23, 33 which so modifies the zone and/or sign fields of the zoned or packed BCD operands that carries can be propagated through those fields, and an output corrector 50 which restores the original zone and/or sign field coding. The sign fields of the two input operands A, B are examined in a sign handler together with the requested add/subtract operation command to control complementing-circuits in the B operand modifier 33 according to whether or not two operands of the same or different signs are to be added or subtracted. In the zoned (EBDIC) format, 4-bit digit fields alternate with 4-bit zone fields coded 1111, the zone field in the lowest order byte being a sign field which is coded 1111 (hex F) for positive and 1101 (hex D) for negative. For operation in zoned format the A operand modifier forces the zone and sign fields to 0000 whereas the B operand modifier forces the sign field to 1111 and leaves the zone fields unchanged at the same code. The digit codes are unchanged for the A operand and are either complemented (for subtraction) or augmented by six (for decimal addition) for the B operand. In the packed BCD format the lowest order 4-bit field is coded 1100 (hex C) for positive and 1101 (hex D) for negative, and the A and B operand modifiers force the sign fields to 0000 and 1111 (hex F) respectively. The adder 20 is a conventional carry look-ahead parallel binary adder (or subtractor), e.g. 4 bytes wide and provides inter-field carries C0-C7. Any odd numbered carry produced from the combination of a pair of zoned digit fields can propagate through the intervening zone field to the next digit field, and a carry in CIN can propagate through the packed BCD sign field to the lowest order digit field. The output corrector 50 has control inputs 26-28, 46 which cause it to force all zone fields to 1111 and/or the sign field to the appropriate code (normally the same as the A operand) as appropriate for zoned or packed BCD operation, and to leave unchanged each digit field or to subtract 6 (or add 10) according to the presence or absence of corresponding carries. In the case where B is numerically greater than A and subtraction is performed, the absence of CO is detected at 65 and causes a recomplementing operation to be performed in which the contents of the output register 53 are loaded into the B register, the A modifier forces all A operand bits to zero, the B modifier complements and the output corrector 50 inverts the original sign of the output. For operation with operands of greater width than the adder, two or more passes are made using different parts of the operands, the operation of modifiers 23, 33 being changed for the second and any subsequent passes to allow for the fact that the sign fields are only present in the first pass. The status of CO is stored in a latch 70 after each pass to form the input CIN for the next pass if any.

公开(公告)号：DE2625113A1

公开(公告)日：1976-12-30

申请号：DE2625113

申请日：1976-06-04

Applicant: IBM

Inventor： GOODING DAVID NORMAN ,  SHIMP EVERETT MONTAGUE

IPC: G06F7/00 ,  G06F11/30 ,  G06F12/14 ,  G06F11/00

Abstract: Data processing circuitry for performing two serially related arithmetic operations during one and the same machine control cycle and employing an independent zone parallel type arithmetic unit capable of simultaneously performing independent arithmetic operations in the different zones thereof. Data transfer circuitry is provided for immediately supplying the output result of a first arithmetic unit zone back to the input of a second arithmetic unit zone for immediately producing a second and different result. Such transfer circuitry is constructed to operate in an asynchronous manner so that the first result is supplied back to the input of the second arithmetic unit zone as soon as it becomes available at the output of the first arithmetic zone. Thus, a second result, which is dependent on the first result, is produced during the same machine control cycle as the first result. This data processing circuitry is particularly useful for providing storage protection for a data processor. In such case, the current storage address and a requested storage access length value are supplied to the first arithmetic unit zone for producing a new address representing the upper extent of the storage access request. The resultant new address is immediately supplied back to the input of the second arithmetic unit zone for combining same with an upper limit address for immediately producing an upper bounds extent error when the new address exceeds the upper limit address.

公开(公告)号：DE2616717A1

公开(公告)日：1976-11-11

申请号：DE2616717

申请日：1976-04-15

Applicant: IBM

Inventor： GOODING DAVID NORMAN ,  SHIMP EVERETT MONTAGUE

IPC: G06F7/505 ,  G06F7/50 ,  G06F7/508

Abstract: A carry look-ahead parallel digital adder having a relatively wide overall data flow width and a pair of automatically adjustable boundary mechanisms for subdividing the adder into plural independent operating zones of variable width and variable location. Anywhere from one to three independent zones may be obtained. Independent external carry-in and carry-out lines are provided for each zone and the connecting points for such lines are automatically shifted in step with the movement of the zone boundaries.