公开(公告)号：DE60205231D1

公开(公告)日：2005-09-01

申请号：DE60205231

申请日：2002-03-28

Applicant: ALCATEL SA ,  IBM

Inventor： BARRI PETER ,  CALVIGNAC JEAN ,  HEDDES MARCO C O IBM UNITED KI ,  LOGAN JOSEPH ,  NIEMEGEERS ALEX ,  VERPLANKEN FABRICE ,  VRANA MIROSLAV

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/18

Abstract: A Network Processor (NP) includes a controller that allows maximum utilization of the memory. The controller includes a memory arbiter that monitors memory access requests from requesters in the NP and awards high priority requesters all the memory bandwidth requested per access to the memory. If the memory bandwidth requested by the high priority requester is less than the full memory bandwidth, the difference between the requested bandwidth and full memory bandwidth is assigned to lower priority requesters. By so doing every memory access utilizes the full memory bandwidth.

公开(公告)号：DE60203785D1

公开(公告)日：2005-05-25

申请号：DE60203785

申请日：2002-02-20

Applicant: IBM

Inventor： CALVIGNAC LOUIS ,  HEDDES MARCO C O IBM UNITED KI ,  LOGAN FRANKLIN ,  VERPLANKEN JEAN

IPC: H04L12/861 ,  H04L29/06 ,  H04L12/56

Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.

公开(公告)号：DE60203785T2

公开(公告)日：2006-03-09

申请号：DE60203785

申请日：2002-02-20

Applicant: IBM

Inventor： CALVIGNAC LOUIS ,  HEDDES MARCO C O IBM UNITED KI ,  LOGAN FRANKLIN ,  VERPLANKEN JEAN

IPC: H04L12/861 ,  H04L29/06

Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.