公开(公告)号：CA2130407A1

公开(公告)日：1995-07-01

申请号：CA2130407

申请日：1994-08-18

Applicant: IBM

Inventor： CHAN FU L ,  HEMANDEZ LUIS A ,  LACROIX NESLY ,  LENTA JORGE E ,  RILEY DWIGHT D ,  TASHAKORI ESMAEIL

IPC: G06F12/08 ,  G06F12/0831 ,  G06F13/362

Abstract: Disclosed is a store in cache having a direct slave interface for eliminating cache data cast out to the main memory. The cache is operative to directly transfer data from a memory location in the cache to a local bus master or an input/output bus master during a read snoop hit cycle. The cache is further operative to invalidate data at a memory location in the cache without casting out the data to the main memory during a write snoop hit cycle. In one embodiment, the cache can be a part of a bus interface controller and coupled directly to a local bus and an input/output bus for selectively communicating with one of the bus masters. In an alternative embodiment, the cache can be an L1 CPU cache or an L2 cache directly coupled to the local bus.