公开(公告)号：CA2065997C

公开(公告)日：1998-02-17

申请号：CA2065997

申请日：1992-04-14

Applicant: IBM

Inventor： HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL ,  FUOCO DANIEL PAUL

IPC: G06F13/38 ,  G06F1/24 ,  G06F13/40 ,  G06F13/20

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.

公开(公告)号：IN179597B

公开(公告)日：1997-10-25

申请号：IN441MA1991

申请日：1991-06-10

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F1/24

公开(公告)号：BR9201917A

公开(公告)日：1993-01-12

申请号：BR9201917

申请日：1992-05-21

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERNANDEZ LUIS A ,  MATHISEN ERIC ,  MOELLER DENNIS L ,  RAYMOND JONATHAN H ,  TASHAKORI ESMAEIL

IPC: G06F1/24 ,  G06F13/00 ,  G06F11/14 ,  G06F13/40

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.

公开(公告)号：AT182697T

公开(公告)日：1999-08-15

申请号：AT92304506

申请日：1992-05-19

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F1/24 ,  G06F13/00

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially requesting such access.

公开(公告)号：CA2064163C

公开(公告)日：1998-04-14

申请号：CA2064163

申请日：1992-03-26

Applicant: IBM

Inventor： FUOCO DANIEL P ,  RAYMOND JONATHAN H ,  MATHISEN ERIC ,  MOELLER DENNIS L ,  HERNANDEZ LUIS A ,  TASHAKORI ESMAEIL

IPC: G06F1/24 ,  G06F13/00

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for continuance of processing through an occurrence of a RESET signal while avoiding systems failures. The personal computer system has a high speed local processor data bus; an input/output data bus; a resettable microprocessor coupled directly to the local processor bus; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and input/output data bus. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus and for arbitration among the input/output data bus and the microprocessor for access to the local processor bus. The bus interface controller further recognizes receipt of a reset signal intended to initiate a reset of the microprocessor and defers delivery of a reset signal to until the bus interface controller has barred access to the local processor bus and input/output bus by any of the devices potentially reqesting such access.

公开(公告)号：SG42881A1

公开(公告)日：1997-10-17

申请号：SG1996000404

申请日：1992-05-19

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/18 ,  G06F13/40

Abstract: This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.

公开(公告)号：CA2130407A1

公开(公告)日：1995-07-01

申请号：CA2130407

申请日：1994-08-18

Applicant: IBM

Inventor： CHAN FU L ,  HEMANDEZ LUIS A ,  LACROIX NESLY ,  LENTA JORGE E ,  RILEY DWIGHT D ,  TASHAKORI ESMAEIL

IPC: G06F12/08 ,  G06F12/0831 ,  G06F13/362

Abstract: Disclosed is a store in cache having a direct slave interface for eliminating cache data cast out to the main memory. The cache is operative to directly transfer data from a memory location in the cache to a local bus master or an input/output bus master during a read snoop hit cycle. The cache is further operative to invalidate data at a memory location in the cache without casting out the data to the main memory during a write snoop hit cycle. In one embodiment, the cache can be a part of a bus interface controller and coupled directly to a local bus and an input/output bus for selectively communicating with one of the bus masters. In an alternative embodiment, the cache can be an L1 CPU cache or an L2 cache directly coupled to the local bus.

公开(公告)号：BR9201915A

公开(公告)日：1993-01-12

申请号：BR9201915

申请日：1992-05-21

Applicant: IBM

Inventor： FUOCO DANIEL P ,  HERNANDEZ LUIS A ,  MATHISEN ERIC ,  MOELLER DENNIS L ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/38 ,  G06F1/24 ,  G06F13/40 ,  G06F13/14

Abstract: This invention relates to personal computers, and more particularly to personal computers in which capability is provided for the usual system controlling processor to be reset, initialized and then isolated if an alternate system controller is provided for the system. In accordance with this invention, a personal computer system has a high speed local processor data bus; an input/output data bus; a microprocessor coupled directly to the local processor bus; a connector coupled directly to the local processor bus for accommodating reception of an alternate processor; and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the local processor bus and the input/output data bus, with the bus interface controller providing for detection of the presence of an alternate processor received in the connector and, in response to detection of the presence of an alternate processor, transferring control of the local processor bus from the microprocessor to the alternate processor.

公开(公告)号：NO922092A

公开(公告)日：1992-11-30

申请号：NO922092

申请日：1992-05-26

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/362 ,  G06F13/40 ,  G06F13/20

CPC classification number: G06F13/362 ,  G06F13/4031

公开(公告)号：NO922091L

公开(公告)日：1992-11-30

申请号：NO922091

申请日：1992-05-26

Applicant: IBM

Inventor： FUOCO DANIEL PAUL ,  HERNANDEZ LUIS ANTONIO ,  MATHISEN ERIC ,  MOELLER DENNIS LEE ,  RAYMOND JONATHAN HENRY ,  TASHAKORI ESMAEIL

IPC: G06F13/36 ,  G06F13/362 ,  G06F13/18 ,  G06F13/20 ,  G06F12/02

Abstract: This invention relates to personal computers, and more particularly to personal computers in which arbitration for control over a data handling bus occurs among a plurality of "master" devices coupled directly to the bus and memory address signals are varied in response to such arbitration. The personal computer system has a high speed local processor data bus, an input/output data bus, a microprocessor coupled directly to the local processor bus, volatile memory coupled to the local processor bus for volatile storage of data, and a bus interface controller coupled directly to the local processor bus and directly to the input/output data bus for providing communications between the buses. The bus interface controller provides for arbitration among devices directly coupled to the input/output data bus for access to the input/output data bus and to the local processor bus, and for arbitration among the input/output data bus and said microprocessor for access to the local processor bus. The bus interface controller is also coupled to the volatile memory for supplying row address select signals to the volatile memory and thereby selecting data storage areas to be accessed, and responds to a change in access granted to the local bus by changing the row address select signal supplied to the volatile memory in preparation for access to potentially different data storage areas of the volatile memory.