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公开(公告)号:US3089123A
公开(公告)日:1963-05-07
申请号:US85232659
申请日:1959-11-12
Applicant: IBM
Inventor: HENNIS ROBERT B , LARSON RUSSELL H
CPC classification number: G06K9/40 , G06K9/38 , G06K2209/01
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公开(公告)号:US3492653A
公开(公告)日:1970-01-27
申请号:US3492653D
申请日:1967-09-08
Applicant: IBM
Inventor: FOSDICK THERON , HAMBURGEN ARTHUR , HENNIS ROBERT B
CPC classification number: G06K9/72 , G06K2209/01
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公开(公告)号:US3408458A
公开(公告)日:1968-10-29
申请号:US41523264
申请日:1964-12-02
Applicant: IBM
Inventor: HENNIS ROBERT B
IPC: G06K7/015
CPC classification number: G06K7/015
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公开(公告)号:US3165717A
公开(公告)日:1965-01-12
申请号:US80499659
申请日:1959-04-08
Applicant: IBM
Inventor: ECKELMAN PAUL F , HENNIS ROBERT B , LARSON RUSSELL H
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公开(公告)号:DE1136861B
公开(公告)日:1962-09-20
申请号:DEJ0019001
申请日:1960-11-11
Applicant: IBM
Inventor: LARSON RUSSEL H , HENNIS ROBERT B
Abstract: 953,443. Automatic character reading. INTERNATIONAL BUSINESS MACHINES CORPORATION. Oct. 31, 1960 [Nov. 12, 1959], No. 37376/60. Heading G4R. In an apparatus for recognising characters printed in magnetic ink, the characters are passed under an A. C. magnetising head 14 (Fig. 1) and sensed by a row of heads 16 and there is circuit means which responds to a signal from the sensing heads of longer than a predetermined duration to give a signal enduring for the whole of a certain time. There are twenty sensing heads of which about ten will be affected by the character, thereby compensating for some out-of-alignment of the character. The twenty channels are reduced to ten in a gating network 20 and the signals amplified at 22. The frequency of the magnetisation is such that a character stroke is represented when sensed by about one cycle of A. C. as shown at I Fig. 2. The characters are specially shaped being formed by strokes and bars in seven vertical columns and ten rows. Signals should ideally appear for periods corresponding to one or two column widths 17, 25 Fig. 2 but owing to defects of printing, voids 407 Fig. 8 irregular edges 404, 405, 406 and specks of ink 408 may distort the signals. To compensate for these distortions the signals are rectified II Fig. 2 and clipped III Fig. 2 and applied to void filling circuits 26. These consist essentially of capacitors 110 Fig. 3 which are charged by the incoming signal through transistor 105 and maintain a transistor 108 in a conducting condition for a period #T1 after the signal has ended. The signals are now as shown in IV Fig. 2 the signals in region 25 distorted due to voids being completed and spurious signals from specks of ink &c. in region 27 being thickened up also by the amount #T1. In the next circuits "subtractor integrators" 28 the periods #T2 and #T3 are subtracted in one step. This is effected by causing the incoming signal to turn off a normally conducting transistor 114 and cause a condenser 115 to discharge. After a time equal to #T2 + #T3 a second normally conducting transistor 117 turns off and produces an output signal at 122. When the incoming signal ceases the first transistor 114 conducts again, charges the condenser 115 instantly and transistor 117 again conducts. The output signal therefore ceases substantially at the same instant as the incoming signal to produce the wave VI Fig. 2. The spurious signals in region 27 which were shorter than #T2 + #T3 have vanished. In a modification this subtraction period is made dependent upon the amplitude of the incoming signal the clipping stage being omitted so that a compensation is made for the apparent change of line width due to the heaviness of printing. A capacitor is charged to a level depending on the incoming signal and is used to vary the bias on the final transistor 117 to vary the time at which it ceases to conduct during discharge of the capacitor 115. A timing circuit control 31 Fig. 1 responds to the appearance of at least two black signals on the set of ten channels to start the timing circuit. This ensures that a start is not given by a spurious signal on the head. The outputs of the subtractor integrator circuits are applied with outputs from the timing circuit to gates in synchronising latch circuits 30 and used to set triggers 34 acting as a buffer for input to the register matrix 36. The timing circuit has two stepping rings of triggers, the first having five steps and the second eight. Each step of the second ring corresponds to one column of the character (seven per character) so that this time is divided into five by the first ring, the signals of which are used to pass each character signal in turn through the buffer triggers. The eight step ring produces pulses to control the entry of the character signals into the register matrix as in Specification 953,442. Recognition circuit 40 and check circuit 42 are also as described in that Specification. The leading edge of the document is sensed by a photocell or brush 15 to generate a resetting pulse..
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公开(公告)号:CA699825A
公开(公告)日:1964-12-15
申请号:CA699825D
Applicant: IBM
Inventor: LARSON RUSSELL H , HENNIS ROBERT B
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公开(公告)号:CA773270A
公开(公告)日:1967-12-05
申请号:CA773270D
Applicant: IBM
Inventor: LARSON RUSSELL H , ECKELMAN PAUL F , HENNIS ROBERT B
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