公开(公告)号：GB2279162B

公开(公告)日：1997-11-19

申请号：GB9312272

申请日：1993-06-15

Applicant: IBM

Inventor： HENRY MICHAEL DAVID ,  LEAVER DAVID ,  WRIGHT-BOULTON NEIL ,  HARE MARK WILLIAM ,  JACKSON FREDERICK SAMUEL

IPC: G06F9/48 ,  G06F13/24 ,  G06F15/78

公开(公告)号：DE69411813T2

公开(公告)日：1999-03-25

申请号：DE69411813

申请日：1994-05-23

Applicant: IBM

Inventor： JACKSON FREDERICK SAMUEL ,  HENRY MICHAEL DAVID ,  LEAVER DAVID ,  WRIGHT-BOULTON NEIL

IPC: G09G1/04 ,  G09G1/16 ,  H03L7/10 ,  H04N5/12

Abstract: Synchronisation apparatus comprises a phase-locked loop (46) for generating an output signal (P) and for synchronising the output signal (P) to an input signal (HSYNC). A controller (44,45) iteratively determines whether the output signal (P) is synchronised to the input signal (HSYNC) by the phase-locked loop (46) and adjusting the frequency of the output signal (P) to locate the output signal (P) within the capture range of the phase-locked loop if the output signal (P) is not synchronised to the input signal (HSYNC). The apparatus can thus maintain the output signal (P) in synchronisation with the input signal (HSYNC) despite large step changes in the frequency of the input signal extending beyond the limits of the capture range of the phase-locked loop. The apparatus is therefore especially useful in display devices for computer systems that can generate video signals corresponding to a number of different display formats.

公开(公告)号：DE69411813D1

公开(公告)日：1998-08-27

申请号：DE69411813

申请日：1994-05-23

Applicant: IBM

Inventor： JACKSON FREDERICK SAMUEL ,  HENRY MICHAEL DAVID ,  LEAVER DAVID ,  WRIGHT-BOULTON NEIL

IPC: G09G1/04 ,  G09G1/16 ,  H03L7/10 ,  H04N5/12

Abstract: Synchronisation apparatus comprises a phase-locked loop (46) for generating an output signal (P) and for synchronising the output signal (P) to an input signal (HSYNC). A controller (44,45) iteratively determines whether the output signal (P) is synchronised to the input signal (HSYNC) by the phase-locked loop (46) and adjusting the frequency of the output signal (P) to locate the output signal (P) within the capture range of the phase-locked loop if the output signal (P) is not synchronised to the input signal (HSYNC). The apparatus can thus maintain the output signal (P) in synchronisation with the input signal (HSYNC) despite large step changes in the frequency of the input signal extending beyond the limits of the capture range of the phase-locked loop. The apparatus is therefore especially useful in display devices for computer systems that can generate video signals corresponding to a number of different display formats.

公开(公告)号：GB2279190A

公开(公告)日：1994-12-21

申请号：GB9312269

申请日：1993-06-15

Applicant: IBM

Inventor： JACKSON FREDERICK SAMUEL ,  HENRY MICHAEL DAVID ,  LEAVER DAVID ,  WRIGHT-BOULTON NEIL

IPC: G09G1/04 ,  G09G1/16 ,  H03L7/10 ,  H04N5/12

Abstract: Synchronisation apparatus comprises a phase-locked loop (46) for generating an output signal (P) and for synchronising the output signal (P) to an input signal (HSYNC). A controller (44,45) iteratively determines whether the output signal (P) is synchronised to the input signal (HSYNC) by the phase-locked loop (46) and adjusting the frequency of the output signal (P) to locate the output signal (P) within the capture range of the phase-locked loop if the output signal (P) is not synchronised to the input signal (HSYNC). The apparatus can thus maintain the output signal (P) in synchronisation with the input signal (HSYNC) despite large step changes in the frequency of the input signal extending beyond the limits of the capture range of the phase-locked loop. The apparatus is therefore especially useful in display devices for computer systems that can generate video signals corresponding to a number of different display formats.

公开(公告)号：GB2279162A

公开(公告)日：1994-12-21

申请号：GB9312272

申请日：1993-06-15

Applicant: IBM

Inventor： HENRY MICHAEL DAVID ,  LEAVER DAVID ,  WRIGHT-BOULTON NEIL ,  HARE MARK WILLIAM ,  JACKSON FREDERICK SAMUEL

IPC: G06F9/48 ,  G06F13/24 ,  G06F15/78

Abstract: An interrupt-driven processor system comprising a processor 10 connected via a plurality of processor input and output lines to an input means 20 in the form of a keypad or keyboard. Actuation of one of the keys of the input means generates an interrupt signal on one of the input lines which invokes an interrupt service routine in the processor. In accordance with the invention, a secondary interrupt source can be attached to each of the input lines with the interrupt service routine being designed to discriminate between an interrupt signal generated by actuation of a key and an interrupt signal generated by a secondary source. Using this technique, further interrupts can be added to an off-the-shelf processor including keypad interrupts without the need for additional interrupt controlling hardware. Furthermore, a custom-built microprocessor can be designed with fewer interrupt pins.