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    Deflection apparatus for raster scanned CRT displays
    4.
    发明专利
    Deflection apparatus for raster scanned CRT displays 未知

    公开(公告)号：GB2278985A

    公开(公告)日：1994-12-14

    申请号：GB9312270

    申请日：1993-06-15

    Applicant: IBM

    Inventor： JACKSON FREDERICK SAMUEL ,  LEAVER DAVID

    IPC: G09G1/04 ,  G09G1/16 ,  H03K4/62 ,  H04N3/27 ,  H04N3/223

    Abstract: A deflection apparatus for a raster scanned cathode ray tube display, the apparatus comprising: a ramp generator having a flyback circuit including a first inductor connected in series with a first transistor switch, the first transistor switch being responsive to a line drive signal to alternately open and close a current path through the first inductor between a first voltage level and a second voltage level lower than the first voltage level to generate a raster scan current signal in a deflection coil of the display, the amplitude of the raster scan current signal being determined as a function of the first voltage level and the frequency of the line drive switching signal, and a boost circuit connected to the flyback circuit, the boost circuit comprising a second inductor connected in series with a second transistor switch, the second transistor switch being responsive to a pulse signal synchronized to the line drive signal to alternately open and close a current path through the second inductor between the second voltage level and a third voltage level higher than the second voltage level to generate the first voltage level, the first voltage level being determined as a function of the third voltage level and the width of the pulses of the pulse signal; and a regulator connected to the flyback circuit and the boost circuit for varying the width of the pulses of the pulse signal as a function of the amplitude of the line scan signal to maintain a constant raster line width as the frequency of the line drive signal is varied.

    Synchronisation apparatus
    6.
    发明专利
    Synchronisation apparatus 未知

    公开(公告)号：GB2279190A

    公开(公告)日：1994-12-21

    申请号：GB9312269

    申请日：1993-06-15

    Applicant: IBM

    Inventor： JACKSON FREDERICK SAMUEL ,  HENRY MICHAEL DAVID ,  LEAVER DAVID ,  WRIGHT-BOULTON NEIL

    IPC: G09G1/04 ,  G09G1/16 ,  H03L7/10 ,  H04N5/12

    Abstract: Synchronisation apparatus comprises a phase-locked loop (46) for generating an output signal (P) and for synchronising the output signal (P) to an input signal (HSYNC). A controller (44,45) iteratively determines whether the output signal (P) is synchronised to the input signal (HSYNC) by the phase-locked loop (46) and adjusting the frequency of the output signal (P) to locate the output signal (P) within the capture range of the phase-locked loop if the output signal (P) is not synchronised to the input signal (HSYNC). The apparatus can thus maintain the output signal (P) in synchronisation with the input signal (HSYNC) despite large step changes in the frequency of the input signal extending beyond the limits of the capture range of the phase-locked loop. The apparatus is therefore especially useful in display devices for computer systems that can generate video signals corresponding to a number of different display formats.

    Interrupt-driven processor system.
    7.
    发明专利
    Interrupt-driven processor system. 未知

    公开(公告)号：GB2279162A

    公开(公告)日：1994-12-21

    申请号：GB9312272

    申请日：1993-06-15

    Applicant: IBM

    Inventor： HENRY MICHAEL DAVID ,  LEAVER DAVID ,  WRIGHT-BOULTON NEIL ,  HARE MARK WILLIAM ,  JACKSON FREDERICK SAMUEL

    IPC: G06F9/48 ,  G06F13/24 ,  G06F15/78

    Abstract: An interrupt-driven processor system comprising a processor 10 connected via a plurality of processor input and output lines to an input means 20 in the form of a keypad or keyboard. Actuation of one of the keys of the input means generates an interrupt signal on one of the input lines which invokes an interrupt service routine in the processor. In accordance with the invention, a secondary interrupt source can be attached to each of the input lines with the interrupt service routine being designed to discriminate between an interrupt signal generated by actuation of a key and an interrupt signal generated by a secondary source. Using this technique, further interrupts can be added to an off-the-shelf processor including keypad interrupts without the need for additional interrupt controlling hardware. Furthermore, a custom-built microprocessor can be designed with fewer interrupt pins.

    8.
    发明专利
    未知

    公开(公告)号：DE69411813T2

    公开(公告)日：1999-03-25

    申请号：DE69411813

    申请日：1994-05-23

    Applicant: IBM

    Inventor： JACKSON FREDERICK SAMUEL ,  HENRY MICHAEL DAVID ,  LEAVER DAVID ,  WRIGHT-BOULTON NEIL

    IPC: G09G1/04 ,  G09G1/16 ,  H03L7/10 ,  H04N5/12

    Abstract: Synchronisation apparatus comprises a phase-locked loop (46) for generating an output signal (P) and for synchronising the output signal (P) to an input signal (HSYNC). A controller (44,45) iteratively determines whether the output signal (P) is synchronised to the input signal (HSYNC) by the phase-locked loop (46) and adjusting the frequency of the output signal (P) to locate the output signal (P) within the capture range of the phase-locked loop if the output signal (P) is not synchronised to the input signal (HSYNC). The apparatus can thus maintain the output signal (P) in synchronisation with the input signal (HSYNC) despite large step changes in the frequency of the input signal extending beyond the limits of the capture range of the phase-locked loop. The apparatus is therefore especially useful in display devices for computer systems that can generate video signals corresponding to a number of different display formats.

    BOOT REQUEST SCHEDULING IN DATA PROCESSING IN DATA PROCESSING NETWORK
    9.
    发明专利
    BOOT REQUEST SCHEDULING IN DATA PROCESSING IN DATA PROCESSING NETWORK 未知

    公开(公告)号：GB2328046A

    公开(公告)日：1999-02-10

    申请号：GB9716796

    申请日：1997-08-08

    Applicant: IBM

    Inventor： JACKSON FREDERICK SAMUEL ,  KNOX RICHARD IAN ,  MCCALL COLIN DAVID

    IPC: G06F9/445

    Abstract: A data processing network comprises a plurality of client systems (30,32,34,36) and a controlling server system (20) operable to issue wake-up requests to the client systems to cause them to issue boot requests onto the network for servicing by a connected server system. The controlling system, which may be embodied in the server system or in a separate system issues the wake-up requests in accordance with a wake-up schedule calculated, for each client, to complete the boot process for that client before a target start-up time when that client user normally uses the client system.

    10.
    发明专利
    未知

    公开(公告)号：DE69411813D1

    公开(公告)日：1998-08-27

    申请号：DE69411813

    申请日：1994-05-23

    Applicant: IBM

    Inventor： JACKSON FREDERICK SAMUEL ,  HENRY MICHAEL DAVID ,  LEAVER DAVID ,  WRIGHT-BOULTON NEIL

    IPC: G09G1/04 ,  G09G1/16 ,  H03L7/10 ,  H04N5/12

    Abstract: Synchronisation apparatus comprises a phase-locked loop (46) for generating an output signal (P) and for synchronising the output signal (P) to an input signal (HSYNC). A controller (44,45) iteratively determines whether the output signal (P) is synchronised to the input signal (HSYNC) by the phase-locked loop (46) and adjusting the frequency of the output signal (P) to locate the output signal (P) within the capture range of the phase-locked loop if the output signal (P) is not synchronised to the input signal (HSYNC). The apparatus can thus maintain the output signal (P) in synchronisation with the input signal (HSYNC) despite large step changes in the frequency of the input signal extending beyond the limits of the capture range of the phase-locked loop. The apparatus is therefore especially useful in display devices for computer systems that can generate video signals corresponding to a number of different display formats.

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