公开(公告)号：CA1268549A

公开(公告)日：1990-05-01

申请号：CA535600

申请日：1987-04-27

Applicant: IBM

Inventor： GRAY KENNETH S ,  HERRMAN BRADLEY D

IPC: G11C29/04 ,  G11C11/401 ,  G11C11/413 ,  G11C29/00 ,  G06F11/20

Abstract: A memory system includes a data storage matrix having columns and rows and a redundant storage matrix having at least one column. The columns of the storage matrix are addressed by column addresses each defining a logical column address for a data bit of a row and corresponding to a predetermined physical column of the storage matrix. The storage matrix is readable in parallel, the parallel read data being serially presented to an output port in a sequence determined by the physical order of the columns of the storage matrix. Column redundancy logic, response to a column address corresponding to a defective physical column of the storage matrix, stores a data bit in a column of the redundant storage matrix. Redundancy control logic response to the column redundancy logic operates on data parallel read from the storage matrix by column addressing, to insert the data bit stored in the redundant column between the data bits read from the data storage matrix according to its logical column address.

公开(公告)号：CA1158741A

公开(公告)日：1983-12-13

申请号：CA377161

申请日：1981-05-08

Applicant: IBM

Inventor： CANNON JACK W ,  HERRMAN BRADLEY D ,  RAMIREZ RAMIRO JR

IPC: G06F13/14 ,  G06F3/02 ,  G06F3/023 ,  G06F3/048 ,  G06F13/38 ,  H03M11/20 ,  H04L5/14

Abstract: BC9-80-001 A central processing unit (CPU) is interconnected with a peripheral device such as an operator console by an interface bus of finite capacity and transfer of information is normally in a preferred direction from the CPU to the console. Provision is made to transfer other information from the console to the CPU without impacting the bus by utilizing a normally continuously operating counter in the CPU and a comparator in the console. The console comparator compares count signals from the CPU console with locally generated digital signals representative of keyboard depressions and provides a stop signal to the CPU counter over a single line when an equal compare occurs. The CPU can then interrogate the CPU counter at a convenient time and confirm a valid entry by operating indicators, such as visual and/or audible means in the console and the interface bus capacity is not impacted by the transfer of the other information from the console.