公开(公告)号：CA1268549A

公开(公告)日：1990-05-01

申请号：CA535600

申请日：1987-04-27

Applicant: IBM

Inventor： GRAY KENNETH S ,  HERRMAN BRADLEY D

IPC: G11C29/04 ,  G11C11/401 ,  G11C11/413 ,  G11C29/00 ,  G06F11/20

Abstract: A memory system includes a data storage matrix having columns and rows and a redundant storage matrix having at least one column. The columns of the storage matrix are addressed by column addresses each defining a logical column address for a data bit of a row and corresponding to a predetermined physical column of the storage matrix. The storage matrix is readable in parallel, the parallel read data being serially presented to an output port in a sequence determined by the physical order of the columns of the storage matrix. Column redundancy logic, response to a column address corresponding to a defective physical column of the storage matrix, stores a data bit in a column of the redundant storage matrix. Redundancy control logic response to the column redundancy logic operates on data parallel read from the storage matrix by column addressing, to insert the data bit stored in the redundant column between the data bits read from the data storage matrix according to its logical column address.

公开(公告)号：DE3865152D1

公开(公告)日：1991-10-31

申请号：DE3865152

申请日：1988-06-28

Applicant: IBM

Inventor： ADAMS ROBERT D ,  FLAKER ROY C ,  GRAY KENNETH S ,  KALTER HOWARD L

IPC: H03K17/08 ,  H03K19/003 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/094 ,  H03K19/0948

Abstract: A CMOS off-chip driver circuit is provided which includes a first P-channel field effect transistor (32) arranged in series with a second or pull-up P-channel transistor (30) and a third P-channel transistor (36) connected from the common point (B) between the first and second transistors (32, 30) and the gate electrode of the first transistor (32). The first and second transistors (32, 30) are disposed between a data output terminal (24) and a first voltage source (28) having a supply voltage of a given magnitude, with the data output terminal (24) also being connected to a circuit or system including a second voltage source having a supply voltage of a magnitude significantly greater than that of the given magnitude. In a more specific aspect of this invention, a fourth P-channel transistor (38), disposed in a common N-well (40) with the other P-channel transistors, is connected at its source to the first voltage source (28) and at its drain to the common N-well, with its gate electrode being connected to the data output terminal.