公开(公告)号：JPH10312282A

公开(公告)日：1998-11-24

申请号：JP7372098

申请日：1998-03-23

Applicant: IBM

Inventor： HOICHII CHON ,  LE HUNG QUI ,  JOHN S MYUHIKU ,  WHITE STEVEN W

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To reduce the restriction of instruction completion by permitting a dispatch unit to dispatch an instruction with condition to an appropriate execution unit through a reserved station associated with the execution unit. SOLUTION: In the case of the regular sequence of the instruction or a sequence having the instruction with condition, a take-out unit takes out a sequence 306 waiting for the instruction from an instruction cache 304 based on a prediction sequence. A decoder unit dispatches the instruction to the appropriate execution units (function units) 308-318 through the reserved stations 324-334 associated with the execution units. A branch instruction is dispatched to the branch unit 308, a storage instruction is dispatched to the storage unit 316 and a fixed point instruction containing a lad instruction is dispatched to a 'cluster' unit 314 and the like. Thus, the restriction of instruction completion can be reduced.

公开(公告)号：JPH10283181A

公开(公告)日：1998-10-23

申请号：JP7616398

申请日：1998-03-24

Applicant: IBM

Inventor： HOICHII CHON ,  LE HUNG QUI ,  JOHN S MYUHIKU ,  WHITE STEVEN W

IPC: G06F9/38 ,  G06F9/46

Abstract: PROBLEM TO BE SOLVED: To provide a method for processing interruption and branching recovery unrelated to the type of generated interruption by dispatching an instruction and source information to an execution queue, judging the propriety of the source information and issuing the instruction for execution in response to the propriety of the source information. SOLUTION: This method is provided with a step for dispatching the instruction and the source information to the execution queue, the step for judging the propriety of the source information and the step for issuing the instruction for the execution in response to the propriety of the source information. For instance, in a processor system, a processor 1210 uses an intrinsic instruction identifier and tracks the program order of the instruction dispatched during random execution. In an execution stage, when an operand and execution resources for an indicated operation become usable, execution units 1222, 1228 and 1230 execute the instruction received from a dispatch unit 1220 conveniently.

公开(公告)号：JPH10283187A

公开(公告)日：1998-10-23

申请号：JP10051298

申请日：1998-03-27

Applicant: IBM

Inventor： HOICHII CHON ,  LE HUNG QUI ,  JOHN S MYUHIKU ,  WHITE STEVEN W

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a method for processing interruption and branching recovery unrelated to the type of generated interruption by writing the identification tag to an item inside an architecture register table in the case that the identification tag of a dispatched instruction is the latest one. SOLUTION: The instruction provided with the identification tag and a relating item inside the architecture register table is dispatched, and in the case that the identification tag of the dispatched instruction is newer than the identification tag of a preceding instruction stored in the item, the identification tag is written to the item inside the architecture register table. In this device, a processor 1210 uses an intrinsic instruction identifier and tracks the program order of the instruction dispatched during random execution. In an execution stage, when an operand and execution resources for an indicated operation become usable, execution units 1222, 1228 and 1230 execute the instruction received from a dispatch unit 1220 conveniently.

公开(公告)号：JPH10283180A

公开(公告)日：1998-10-23

申请号：JP7587898

申请日：1998-03-24

Applicant: IBM

Inventor： HOICHII CHON ,  LE HUNG QUI ,  JOHN S MYUHIKU ,  WHITE STEVEN W

IPC: G06F9/38

Abstract: PROBLEM TO BE SOLVED: To provide a method for processing interruption and branching recovery unrelated to the type of generated interruption by providing a step for allocating an identification tag to an instruction and the step for dispatching the instruction, the identification tag and source information to an execution queue. SOLUTION: This method is provided with the step for allocating the identification tag to the instruction and the step for dispatching the instruction, the identification tag and the source information to the execution queue. Such a tag system provides an integrated mechanism for supporting complete random execution. For instance, in a processor system, a processor 1210 uses an intrinsic instruction identifier and tracks the program order of the instruction dispatched during random execution. In an execution stage, when an operand and execution resources for an indicated operation become usable, execution units 1222, 1228 and 1230 execute the instruction received from a dispatch unit 1220 conveniently.