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公开(公告)号：JPH10283181A
公开(公告)日：1998-10-23
申请号：JP7616398
申请日：1998-03-24
Applicant: IBM
Inventor： HOICHII CHON , LE HUNG QUI , JOHN S MYUHIKU , WHITE STEVEN W
Abstract: PROBLEM TO BE SOLVED: To provide a method for processing interruption and branching recovery unrelated to the type of generated interruption by dispatching an instruction and source information to an execution queue, judging the propriety of the source information and issuing the instruction for execution in response to the propriety of the source information. SOLUTION: This method is provided with a step for dispatching the instruction and the source information to the execution queue, the step for judging the propriety of the source information and the step for issuing the instruction for the execution in response to the propriety of the source information. For instance, in a processor system, a processor 1210 uses an intrinsic instruction identifier and tracks the program order of the instruction dispatched during random execution. In an execution stage, when an operand and execution resources for an indicated operation become usable, execution units 1222, 1228 and 1230 execute the instruction received from a dispatch unit 1220 conveniently.
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公开(公告)号：JPH10312282A
公开(公告)日：1998-11-24
申请号：JP7372098
申请日：1998-03-23
Applicant: IBM
Inventor： HOICHII CHON , LE HUNG QUI , JOHN S MYUHIKU , WHITE STEVEN W
IPC: G06F9/38
Abstract: PROBLEM TO BE SOLVED: To reduce the restriction of instruction completion by permitting a dispatch unit to dispatch an instruction with condition to an appropriate execution unit through a reserved station associated with the execution unit. SOLUTION: In the case of the regular sequence of the instruction or a sequence having the instruction with condition, a take-out unit takes out a sequence 306 waiting for the instruction from an instruction cache 304 based on a prediction sequence. A decoder unit dispatches the instruction to the appropriate execution units (function units) 308-318 through the reserved stations 324-334 associated with the execution units. A branch instruction is dispatched to the branch unit 308, a storage instruction is dispatched to the storage unit 316 and a fixed point instruction containing a lad instruction is dispatched to a 'cluster' unit 314 and the like. Thus, the restriction of instruction completion can be reduced.
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3.发明专利
公开(公告)号：JPH10283179A
公开(公告)日：1998-10-23
申请号：JP7380398
申请日：1998-03-23
Applicant: IBM
Inventor： JORDAN PAUL J , KONIGSBURG BRIAN R , LE HUNG QUI , WHITE STEVEN W
IPC: G06F9/38
Abstract: PROBLEM TO BE SOLVED: To provide a pipeline type data processor for performing the random execution and inference execution of instructions by allocating intrinsic identifiers to the respective instructions and using the identifiers again during the execution of a program inside a data processing system. SOLUTION: This data processing system is provided with an input circuit and a memory for storing plural control values corresponding to the identifiers of plural targets and the memory is provided with first and second banks. Also, a target identification circuit for generating plural target identification values and continuously allocating the respective target identifiers to the corresponding instructions is provided as well. When the target identification values corresponding to the plural control values are allocated inside the first and second banks, the target identification circuit selectively reallocates the first part of the plural target identification values corresponding to the first part of the plural control values inside the first bank. The data processing system 100 is provided with a pipeline type CPU 110 and the CPU 110 is connected to other various constituting elements by a system bus 112.
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公开(公告)号：JPH10283187A
公开(公告)日：1998-10-23
申请号：JP10051298
申请日：1998-03-27
Applicant: IBM
Inventor： HOICHII CHON , LE HUNG QUI , JOHN S MYUHIKU , WHITE STEVEN W
IPC: G06F9/38
Abstract: PROBLEM TO BE SOLVED: To provide a method for processing interruption and branching recovery unrelated to the type of generated interruption by writing the identification tag to an item inside an architecture register table in the case that the identification tag of a dispatched instruction is the latest one. SOLUTION: The instruction provided with the identification tag and a relating item inside the architecture register table is dispatched, and in the case that the identification tag of the dispatched instruction is newer than the identification tag of a preceding instruction stored in the item, the identification tag is written to the item inside the architecture register table. In this device, a processor 1210 uses an intrinsic instruction identifier and tracks the program order of the instruction dispatched during random execution. In an execution stage, when an operand and execution resources for an indicated operation become usable, execution units 1222, 1228 and 1230 execute the instruction received from a dispatch unit 1220 conveniently.
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Patent Agency Ranking
公开(公告)号：JPH10283180A
公开(公告)日：1998-10-23
申请号：JP7587898
申请日：1998-03-24
Applicant: IBM
Inventor： HOICHII CHON , LE HUNG QUI , JOHN S MYUHIKU , WHITE STEVEN W
IPC: G06F9/38
Abstract: PROBLEM TO BE SOLVED: To provide a method for processing interruption and branching recovery unrelated to the type of generated interruption by providing a step for allocating an identification tag to an instruction and the step for dispatching the instruction, the identification tag and source information to an execution queue. SOLUTION: This method is provided with the step for allocating the identification tag to the instruction and the step for dispatching the instruction, the identification tag and the source information to the execution queue. Such a tag system provides an integrated mechanism for supporting complete random execution. For instance, in a processor system, a processor 1210 uses an intrinsic instruction identifier and tracks the program order of the instruction dispatched during random execution. In an execution stage, when an operand and execution resources for an indicated operation become usable, execution units 1222, 1228 and 1230 execute the instruction received from a dispatch unit 1220 conveniently.
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公开(公告)号：CA2453685A1
公开(公告)日：2005-06-17
申请号：CA2453685
申请日：2003-12-17
Applicant: IBM CANADA
Inventor： VEZOLLE PASCAL , WHITE STEVEN W , ARCHAMBAULT ROCH G , O'CONNELL FRANCIS P , GAO YAOQING , MCCALPIN JOHN D , BLAINEY ROBERT J
Abstract: A method and system of modifying instructions forming a loop is provided. A method of modifying instructions forming a loop includes modifying instructions formin g a loop including: determining static and dynamic characteristics for the instructions; selecti ng a modification factor for the instructions based on a number of separate equivalent sections formi ng a cache in a processor which is processing the instructions; and modifying the instructio ns to interleave the instructions in the loop according to the modification factor and the static and dynamic characteristics when the instructions satisfy a modification criteria based on the static and dynamic characteristics.
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公开(公告)号：CA2005463C
公开(公告)日：1995-06-27
申请号：CA2005463
申请日：1989-12-13
Applicant: IBM
Inventor： WHITE STEVEN W
IPC: G06F12/10
Abstract: A dynamic address translation mechanism includes a first directory-look-aside-table (DLAT) for 4KB page sizes and a second DLAT for 1MB page sizes. The page size does need not be known prior to DLAT presentation. When a virtual address is presented for translation, it is applied simultaneously to both DLATs for translation by either DLAT if it contains a page address entry corresponding to the virtual address presented. If a DLAT "miss" occurs, segment/page table searching is initiated. The DLAT page sizes are preferably made equal to the segment/page sizes and placed on 4KB and 1MB boundaries. Virtual page addresses lie within either a 1MB page or a 4KB page, and an entry for any virtual address can exist in only one (not both) of the DLATs.
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公开(公告)号：CA2363182C
公开(公告)日：2006-06-06
申请号：CA2363182
申请日：2001-11-19
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT J , HALL BRIAN C , WHITE STEVEN W
Abstract: A method, a computer or computer program product for automatically restructuring a program having arrays in inner loops to reduce an average penalty incurred for burst y cache miss patterns by spreading out the cache misses. The method may be used separately or in conjunction with methods for reducing the number of cache misses. The method determines a padding required for each array according to a proportion of the cache line size, to offset the starting points of the arrays relative to the start of a cache line memory access address for each array. Preferably, the starting points of the arrays that induce bursty cache misses are padded so that they are uniformly spaced from one another.
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公开(公告)号：CA2363182A1
公开(公告)日：2003-05-19
申请号：CA2363182
申请日：2001-11-19
Applicant: IBM CANADA
Inventor： BLAINEY ROBERT J , HALL BRIAN C , WHITE STEVEN W
Abstract: A method, a computer or computer program product for automatically restructuring a program having arrays in inner loops to reduce an average penalty incurred for burst y cache miss patterns by spreading out the cache misses. The method may be used separately or in conjunction with methods for reducing the number of cache misses. The method determines a padding required for each array according to a proportion of the cache line size, to offset the starting points of the arrays relative to the start of a cache line memory access address for each array. Preferably, the starting points of the arrays that induce bursty cache misses are padded so that they are uniformly spaced from one another.
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