公开(公告)号：JPH10178180A

公开(公告)日：1998-06-30

申请号：JP28834797

申请日：1997-10-21

Applicant: IBM

Inventor： PAUL MICHAEL SOLOMON ,  HON-SUMU PHILIP WONG

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To ensure the high duplicatability of a single gate and dual gate field-effect transistor by a method wherein a top gate and the like and insulating sidewall layers are formed on a channel layer provided with drain and source regions, amorphous silicon sidewalls are respectively formed adjacent to the insulating sidewall layers and a gate pillar and the insulating sidewall layers are etched using these amorphous silicon sidewall as masks. SOLUTION: An FET 10 is positioned on a substrate 11 and a channel region 15, a source region 20.1 and a drain region 20.2 are positioned on an insulator 14. An insulator 22 is provided between a top gate 21 and the channel gate 15. A gate pillar 19 consisting of a silicon nitride film is formed on the top gate 21 consisting of a tungsten film and the sidewall of the gate pillar 19 are respectively covered with sidewall insulators 18.1 and 18.2 consisting of an SiO2 film. Extension parts 17.1 and 17.2 of the source sidewall and the drain sidewall are formed on an amorphous silicon film and are placed on each region of these regions 20.1 and 20.2. A source contact 16.1 and a drain contact 16.2 are formed of a metal silicide film and respectively come into contact with each extension part of the extension parts. The gate pillar and the sidewall insulators are etched using four lithographic masks.