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    SELF-ALIGNED SILICIDE PROCESS AND STRUCTURE FORMED USING IT
    1.
    发明专利
    SELF-ALIGNED SILICIDE PROCESS AND STRUCTURE FORMED USING IT 审中-公开

    公开(公告)号：JP2002353246A

    公开(公告)日：2002-12-06

    申请号：JP2002110367

    申请日：2002-04-12

    Applicant: IBM

    Inventor： CYRILLE CABRAL JR ,  KEVIN K CHAN ,  COHEN GUY MOSHE ,  GUARINI KATHRYN WILDER ,  LAVOIE CHRISTIAN ,  PAUL MICHAEL SOLOMON ,  ZHANG YING

    IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L29/45 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To provide a self-aligned silicide process applicable to contacting silicon, sidewall, source, and drain. SOLUTION: A method (and a structure formed by using this method) to form a metal silicide contact on a non-planar silicon-containing area which limits the silicon consumption at a silicon-containing area includes: forming a blanket metal layer over the silicon-containing area, forming a silicon layer over the metal layer, performing an selective and anisotropical etching of the silicon layer against the metal, forming a metal silicon alloy by reacting the metal and silicon at a first temperature, etching away any unreacted metal layer, forming a metal-Si2 alloy by annealing at a second temperature, and selectively etching away any unreacted silicon layer.

    EEPROM
    2.
    发明专利
    EEPROM 失效

    公开(公告)号：JPH1065031A

    公开(公告)日：1998-03-06

    申请号：JP16720197

    申请日：1997-06-24

    Applicant: IBM

    Inventor： ALEKSANDR AKOBUITSUTSU ,  TAKU FUN NIN ,  PAUL MICHAEL SOLOMON

    IPC: H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device suitable for an electrically erasable and programmable read-only memory(EEPROM), an array of such device and a stacked array of such device. SOLUTION: An EEPROM device takes in a field-effect transistor and a control gate being spacing arranged on a first insulating layer, a second insulating layer formed on the field-effect transistor and the control gate and a common floating gate on the second insulating layer and on a channel of the field- effect transistor, accordingly this floating gate forms also a gate electrode of the field-effect transistor. This EEPROM device allows an interconnection inside a memory array and mutual overlapping of a plurality of memory arrays. Thereby, a problem at the time of forming an EEPROM array with high spatial density can be overcome by using a nonstandard silicon on insulator(SOI) CMOS process.

    SINGLE GATE AND DUAL GATE FIELD-EFFECT TRANSISTOR AND FORMATION
    4.
    发明专利
    SINGLE GATE AND DUAL GATE FIELD-EFFECT TRANSISTOR AND FORMATION 失效

    公开(公告)号：JPH10178180A

    公开(公告)日：1998-06-30

    申请号：JP28834797

    申请日：1997-10-21

    Applicant: IBM

    Inventor： PAUL MICHAEL SOLOMON ,  HON-SUMU PHILIP WONG

    IPC: H01L21/336 ,  H01L29/417 ,  H01L29/786

    Abstract: PROBLEM TO BE SOLVED: To ensure the high duplicatability of a single gate and dual gate field-effect transistor by a method wherein a top gate and the like and insulating sidewall layers are formed on a channel layer provided with drain and source regions, amorphous silicon sidewalls are respectively formed adjacent to the insulating sidewall layers and a gate pillar and the insulating sidewall layers are etched using these amorphous silicon sidewall as masks. SOLUTION: An FET 10 is positioned on a substrate 11 and a channel region 15, a source region 20.1 and a drain region 20.2 are positioned on an insulator 14. An insulator 22 is provided between a top gate 21 and the channel gate 15. A gate pillar 19 consisting of a silicon nitride film is formed on the top gate 21 consisting of a tungsten film and the sidewall of the gate pillar 19 are respectively covered with sidewall insulators 18.1 and 18.2 consisting of an SiO2 film. Extension parts 17.1 and 17.2 of the source sidewall and the drain sidewall are formed on an amorphous silicon film and are placed on each region of these regions 20.1 and 20.2. A source contact 16.1 and a drain contact 16.2 are formed of a metal silicide film and respectively come into contact with each extension part of the extension parts. The gate pillar and the sidewall insulators are etched using four lithographic masks.

    Field effect transistor with controllable resistance
    5.
    发明专利
    Field effect transistor with controllable resistance 未知

    公开(公告)号：GB2583299A

    公开(公告)日：2020-10-21

    申请号：GB202010141

    申请日：2018-12-19

    Applicant: IBM

    Inventor： YULONG LI ,  PAUL MICHAEL SOLOMON ,  SIYURANGA O KOSWATTA

    IPC: H01L27/098

    Abstract: Embodiments of the invention are directed to a method and resulting structures for a semiconductor device having a controllable resistance. An example method for forming a semiconductor device includes forming a source terminal and a drain terminal of a field effect transistor (FET) on a substrate. The source terminal and the drain terminal are formed on either sides of a channel region. An energy barrier is formed adjacent to the source terminal and the channel region. A conductive gate is formed over the channel region.

    Field effect transistor with controllable resistance
    6.
    发明专利
    Field effect transistor with controllable resistance 未知

    公开(公告)号：GB2583299B

    公开(公告)日：2022-05-04

    申请号：GB202010141

    申请日：2018-12-19

    Applicant: IBM

    Inventor： YULONG LI ,  PAUL MICHAEL SOLOMON ,  SIYURANGA O KOSWATTA

    IPC: H01L27/098

    Abstract: A method and resulting structures for a semiconductor device includes forming a source terminal of a semiconductor fin on a substrate. An energy barrier is formed on a surface of the source terminal. A channel is formed on a surface of the energy barrier, and a drain terminal is formed on a surface of the channel. The drain terminal and the channel are recessed on either sides of the channel, and the energy barrier is etched in recesses formed by the recessing. The source terminal is recessed using timed etching to remove a portion of the source terminal in the recesses formed by etching the energy barrier. A first bottom spacer is formed on a surface of the source terminal and a sidewall of the semiconductor fin, and a gate stack is formed on the surface of the first bottom spacer.

    Counter based resistive processing unit for programmable and reconfigurable artificial-neural-networks
    7.
    发明专利
    Counter based resistive processing unit for programmable and reconfigurable artificial-neural-networks 未知

    公开(公告)号：GB2582088B

    公开(公告)日：2022-07-27

    申请号：GB202007432

    申请日：2018-11-22

    Applicant: IBM

    Inventor： YULONG LI ,  SIYURANGA O KOSWATTA ,  PAUL MICHAEL SOLOMON

    IPC: G06N3/08 ,  G06N3/063

    Abstract: Technical solutions are described for storing weight in a crosspoint device of a resistive processing unit (RPU) array. An example system includes a crosspoint array, wherein each array node represents a connection between neurons of the neural network, and wherein each node stores a weight assigned to the node. The crosspoint array includes a crosspoint device at each node. The crosspoint device includes a counter that has multiple single bit counters, and states of the counters represent the weight to be stored at the crosspoint device. Further, the crosspoint device includes a resistor device that has multiple resistive circuits, and each resistive circuit is associated with a respective counter from the counters. The resistive circuits are activated or deactivated according to a state of the associated counter, and an electrical conductance of the resistor device is adjusted based at least in part on the resistive circuits that are activated.

    Counter based resistive processing unit for programmable and reconfigurable artificial-neural-networks
    8.
    发明专利
    Counter based resistive processing unit for programmable and reconfigurable artificial-neural-networks 未知

    公开(公告)号：GB2582088A

    公开(公告)日：2020-09-09

    申请号：GB202007432

    申请日：2018-11-22

    Applicant: IBM

    Inventor： YULONG LI ,  SIYURANGA O KOSWATTA ,  PAUL MICHAEL SOLOMON

    IPC: G06N3/08 ,  G06N3/063

    Abstract: Technical solutions are described for storing weight in a crosspoint device of a resistive processing unit (RPU) array. An example method includes setting a state of each single bit counter from a set of single bit counters in the crosspoint device, the states of the single bit counters representing the weight to be stored at the crosspoint device. The method further includes adjusting electrical conductance of a resistor device of the crosspoint device. The resistor device includes a set of resistive circuits, each resistive circuit associated with a respective single bit counter from the set of single bit counters, the electrical conductance adjusted by activating or deactivating each resistive circuit according to a state of the associated single bit counter.

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