公开(公告)号：JPS61281721A

公开(公告)日：1986-12-12

申请号：JP8841886

申请日：1986-04-18

Applicant: IBM

Inventor： HONG JU-HI JOHN

IPC: H04J9/00 ,  G06F11/10 ,  H03M5/02 ,  H03M13/00 ,  H03M13/37 ,  H03M13/45 ,  H04L1/24 ,  H04L25/06 ,  H04L25/497

公开(公告)号：DE2619964A1

公开(公告)日：1976-11-25

申请号：DE2619964

申请日：1976-05-06

Applicant: IBM

Inventor： GINDI ABRAHAM ,  HONG JU-HI JOHN ,  STELZENMULLER WILLIAM KARL ,  POUGHKEEPSIE N Y

IPC: H03M5/12 ,  H03K5/00 ,  H03L7/00 ,  H04J3/06 ,  H04L5/22 ,  H04L7/00 ,  H04L7/033 ,  H04L25/40 ,  H04L25/49 ,  H04Q11/04 ,  H04L25/08 ,  H03K13/01

Abstract: An improved clock retiming system for pulse coded data is provided in which the clock signals are extracted from the encoded data and first and second signals of the same amplitude and frequency but of different phase are generated from the clock signals. First and second amplifiers having variable gains provide amplification for the first and second signals, respectively. The first and second amplified signals are summed to produce a third signal having a phase which is a function of the relative amplitudes of the first and second amplified signals. The original pulse encoded data is sampled with the third signal to produce the retimed data output. The original pulse encoded data is also utilized to sample the third signal. The resulting signal is filtered to provide a DC voltage feedback error signal indicative of the phase difference between the third signal and the original pulse encoded data. This feedback signal is translated into a pair of complementary signals forming inputs to the first and second amplifiers, respectively, to vary the variable gains thereof, oppositely thereby adjusting the phase of the third signal to correspond to the phase of the original pulse encoded data.

公开(公告)号：DE3685914T2

公开(公告)日：1993-02-25

申请号：DE3685914

申请日：1986-04-21

Applicant: IBM

Inventor： HONG JU-HI JOHN

IPC: H04J9/00 ,  G06F11/10 ,  H03M5/02 ,  H03M13/00 ,  H03M13/37 ,  H03M13/45 ,  H04L1/24 ,  H04L25/06 ,  H04L25/497 ,  H04L25/30

Abstract: An error correcting scheme for processing data which is transmitted on a broadcast and/or CATV network and utilizes the IEEE 802.4 three-level duobinary AM/PSK (phase shift keying) coding format. The error correcting scheme utilizes two thresholders. One of the thresholders makes data (1 or 0) decisions while the other thresholder makes non-data or no non-data (non-data) decisions. Pattern matching and windowing are used to detect non-data symbols which are corrected if the non-data symbols deviate from a predetermined pattern. The template used in the pattern matching is determined from the state of a demodulator.

公开(公告)号：DE3685914D1

公开(公告)日：1992-08-13

申请号：DE3685914

申请日：1986-04-21

Applicant: IBM

Inventor： HONG JU-HI JOHN

IPC: H04J9/00 ,  G06F11/10 ,  H03M5/02 ,  H03M13/00 ,  H03M13/37 ,  H03M13/45 ,  H04L1/24 ,  H04L25/06 ,  H04L25/497 ,  H04L25/30

Abstract: An error correcting scheme for processing data which is transmitted on a broadcast and/or CATV network and utilizes the IEEE 802.4 three-level duobinary AM/PSK (phase shift keying) coding format. The error correcting scheme utilizes two thresholders. One of the thresholders makes data (1 or 0) decisions while the other thresholder makes non-data or no non-data (non-data) decisions. Pattern matching and windowing are used to detect non-data symbols which are corrected if the non-data symbols deviate from a predetermined pattern. The template used in the pattern matching is determined from the state of a demodulator.

公开(公告)号：DE3070957D1

公开(公告)日：1985-09-12

申请号：DE3070957

申请日：1980-11-20

Applicant: IBM

Inventor： HONG JU-HI JOHN

IPC: H02H3/24 ,  C03B9/41 ,  H03K5/02 ,  H03K17/082

Abstract: A monolithic integrated protection circuit is provided in which the output voltage (V OUT) is sensed and the output device (10) is shut-off for protection when the output voltage falls below a predetermined trip voltage. The circuit includes a voltage shifting circuit (42) for transferring the output voltage to a biasing circuit which biases a switching circuit (32) which turns the line driver (10) off when an overload or short circuit causes a voltage drop below a predetermined trip voltage. The protection circuit is disabled during start-up or signal rise time by splitting the input signal into two separate paths (29, 30 and 48, 46) in which the signals have different delays, the shorter delay allowing the input signal to rise and to appear on the output line before the longer delay input signal rises enabling the protection circuit.