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    Dram circuit and its operating method
    2.
    发明专利
    Dram circuit and its operating method 有权
    DRAM电路及其工作方法

    公开(公告)号：JP2004110979A

    公开(公告)日：2004-04-08

    申请号：JP2002274432

    申请日：2002-09-20

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： HOSOKAWA KOJI ,  MORI YOTARO

    IPC: H01L21/8242 ,  G11C7/18 ,  G11C11/401 ,  G11C11/4097 ,  H01L27/108

    CPC classification number: G11C11/4097 ,  G11C7/18

    Abstract: PROBLEM TO BE SOLVED: To provide a DRAM of an MTBL system in which interference noise between bit lines is reduced and density is high.
    SOLUTION: Duplication of a sense amplifier (SA) and a bit switch (BSW) in a conventional MTBL system is eliminated, one line of a sense amplifier and a bit switch (BSW/SA) is arranged between each cell area. That is, an array is shifted in the transverse direction and piled vertically, and area is reduced. A pair of bit lines connected every other one in sense amplifiers (SA) arranged in transverse one line is replaced alternately up and down. In a pair of bit lines 11, intersection is performed at one place and interval of bit lines is made wider from the intersection point. Also, in a pair of bit lines 16, intersection is not caused, interval of bit lines is made wider at a half way. In a new MTBL system, in both cases of bit lines connected to the same sense amplifier and bit lines connected to different sense amplifiers out of adjacent bit lines, interval of the bit lines is varied (wider or narrower) at before or after the intersection point. Therefore, interference noise between adjacent any bit lines is reduced.
    COPYRIGHT: (C)2004,JPO

    Abstract translation: 要解决的问题：提供其中位线之间的干扰噪声降低并且密度高的MTBL系统的DRAM。 解决方案：消除了常规MTBL系统中的读出放大器（SA）和位开关（BSW）的复制，读取放大器和位开关（BSW / SA）的一行布置在每个单元区域之间。 也就是说，阵列在横向上移动并垂直堆叠，并且面积减小。 在横向一行排列的读出放大器（SA）中每隔一个地连接的一对位线被交替上下替换。 在一对位线11中，在一个位置进行交叉，并且从交点开始位线的间隔更宽。 此外，在一对位线16中，没有引起交叉，位线的间隔在一半处变宽。 在新的MTBL系统中，在连接到相同读出放大器的位线和连接到相邻位线之间的不同读出放大器的位线的两种情况下，位线之​​间的间隔在交点之前或之后变化（更宽或更窄） 点。 因此，相邻任何位线之间的干扰噪声减小。 版权所有（C）2004，JPO

    DEFECT RELIEVING DISCRIMINATING CIRCUIT FOR SEMICONDUCTOR MEMORY AND METHOD THEREFOR
    4.
    发明专利
    DEFECT RELIEVING DISCRIMINATING CIRCUIT FOR SEMICONDUCTOR MEMORY AND METHOD THEREFOR 失效

    公开(公告)号：JP2001057099A

    公开(公告)日：2001-02-27

    申请号：JP22838599

    申请日：1999-08-12

    Applicant: IBM

    Inventor： HOSOKAWA KOJI

    IPC: G06F12/16 ,  G11C29/00 ,  G11C29/04 ,  G11C29/44

    Abstract: PROBLEM TO BE SOLVED: To speed up the defect relieving discrimination operation of a semiconductor memory. SOLUTION: In this defect relieving discriminating circuit, the circuit configuration of a comparing and discriminating circuit 3' is simplified and a comparison and discrimination operation is speeded up by holding previously an output (program information) of a program information holding circuit 1 at the time of finish of previous operation in an address information updating holding circuit 2' as address information, before an address of the address information updating and holding circuit 2' is updated and held.

    WRITE-DRIVER OF DRAM
    5.
    发明专利
    WRITE-DRIVER OF DRAM 失效

    公开(公告)号：JP2002298581A

    公开(公告)日：2002-10-11

    申请号：JP2001098160

    申请日：2001-03-30

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO ,  HOSOKAWA KOJI

    IPC: G11C11/409 ,  G11C11/407

    Abstract: PROBLEM TO BE SOLVED: To provide a write-driver of a DRAM in which operation speed of a write-in cycle of a DRAM is increased, erroneous write-in for a cell not to be written is prevented, and which performs stable write-in. SOLUTION: This write-driver of a DRAM 10 comprises nMOSFET 16c, 16d in which a signal indicating write-in of '1' or '0' is inputted to a gate and data line is connected to a drain, pMOSFET 14c, 14d in which a signal indicating pre-charge of a sense amplifier is inputted to a gate, a power source is connected to a source, and drains are connected to sources of the nMOSFET 16c, 16d, and capacitors Cw0, Cw1 in which sources of the nMOSFET 16c, 16d and drains of the pMOSFET 14c, 14d are connected to ground.

    DRAM ARRAY
    6.
    发明专利
    DRAM ARRAY 失效

    公开(公告)号：JPH09139075A

    公开(公告)日：1997-05-27

    申请号：JP28384995

    申请日：1995-10-31

    Applicant: IBM

    Inventor： SUNANAGA TOSHIO ,  HOSOKAWA KOJI

    IPC: G11C11/41 ,  G11C7/10 ,  G11C11/401 ,  G11C11/407 ,  G11C11/409

    Abstract: PROBLEM TO BE SOLVED: To simultaneously accelerate RAS access time and a data transfer rate for the acceleration of a DRAM. SOLUTION: This DRAM array is provided with a row decoder means 2 and a column decoder means 3 respectively connected to the word line and bit line of a cell matrix part 1 and the column decoder means 3 is provided with plural bit switches 44 and 46 for connecting a prescribed bit line to an output bus and a local latch 36 for storing data bits provided in each group 32 of the bit lines which is the unit of the prescribed number of the bit lines. The bit switch is provided with a hierarchical structure, and since the bit line and the output bus are connected through the two serially connected bit switches, the load capacity of data lines 52 and 56 is reduced. Data inside the respective local latches 36 are serially stored in a local buffer 74 in a prescribed order and fast burst transfer is made possible.

    DRAM CIRCUIT AND ITS CONTROL METHOD
    7.
    发明专利
    DRAM CIRCUIT AND ITS CONTROL METHOD 失效

    公开(公告)号：JP2001250380A

    公开(公告)日：2001-09-14

    申请号：JP2000059279

    申请日：2000-03-03

    Applicant: IBM

    Inventor： HOSOKAWA KOJI

    IPC: G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C11/409

    Abstract: PROBLEM TO BE SOLVED: To provide a DRAM circuit with which operation speed of writing can be increased even when a write-mask is performed and its control method. SOLUTION: This DRAM circuit has a new column switch 14 for connecting a bit-line-pair 12 and a data-line pair 5 through a sense amplifier 13. This new column switch has a function for separating the data-line-pair 15 selected in write-mask-operation from the corresponding bit-line-pair 12. Consequently, even if the column switch 14 is turned on before it is sufficiently amplified by the sense amplifier 13, there in no possibility that the sense amplifier 13 is erroneously operated and data on the bit-line-pair 12 is destroyed operating speed of writing can be increased independently of existence of write-mask- operation of a DRAM.

    SENSE AMPLIFIER
    8.
    发明专利
    SENSE AMPLIFIER 失效

    公开(公告)号：JP2001084767A

    公开(公告)日：2001-03-30

    申请号：JP24296699

    申请日：1999-08-30

    Applicant: IBM

    Inventor： HOSOKAWA KOJI

    IPC: G11C11/409 ,  G11C7/06 ,  G11C11/4091

    Abstract: PROBLEM TO BE SOLVED: To provide a sense amplifier that can achieve high-speed amplification and high-speed rewrite of a memory. SOLUTION: In the sense amplifier for detecting the potential difference between a pair of signal lines BM (BL) and /BM (/BL) for amplifying, first pull-down circuits N20 and N21, pull-up circuits P10 and P11, and second pull- down circuits N28 and N29 are arranged successively between the pair of signal lines. The pull-up circuits P10 and P11 include a pair of P-type FETs P10 and P11 for composing a flip-flop, and the sources of the pair of P-type FETs are connected directly to a first constant-voltage source Vd.

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