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    Microprogrammed processor with variable basic machine cycle lengths
    2.
    发明授权
    Microprogrammed processor with variable basic machine cycle lengths 失效
    具有可变基本机器循环长度的微处理器

    公开(公告)号：US3656123A

    公开(公告)日：1972-04-11

    申请号：US3656123D

    申请日：1970-04-16

    Applicant: IBM

    Inventor： CARNEVALE RICHARD J ,  HOWE LELAND D JR ,  METZ THOMAS A ,  WOMACK KARL K ,  ZURLA FRANK A

    IPC: G06F9/22 ,  G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/12

    CPC classification number: G06F9/30192 ,  G06F9/223 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/3869

    Abstract: A microprogrammed processor has a single storage unit for both main store and control store wherein the read/write times of the storage unit are less than the time required for the microprogram controlled hardware to execute a control word. Since there is no requirement for the hardware to wait for a next succeeding access to storage as in typical known processors, but rather the storage unit now waits for the hardware, it becomes feasible and practicable to improve the performance of the processor significantly with little additional cost by providing basic machine cycle times for different control word executions which are maintained at a minimum. In the preferred embodiment, a decode circuit examines each control word after it is transferred from control store to a control register to determine the word type which is to be executed. Depending upon the word type, the decode circuitry applies control pulses to the processor clock to cause ti to produce a selected one of three available cycle lengths or a combination of two of said three available cycle lengths. In this manner, system performance is significantly improved.

    Abstract translation: 微程序处理器具有用于主存储和控制存储的单个存储单元，其中存储单元的读/写时间小于微程序控制的硬件执行控制字所需的时间。 由于硬件不需要像在典型的已知处理器中等待下一次成功访问存储，而是存储单元现在等待硬件，因此显着地提高处理器的性能变得可行和可行 通过为保持最小的不同控制字执行提供基本的机器周期时间来降低成本。 在优选实施例中，解码电路在从控制存储器传送到控制寄存器之后检查每个控制字以确定要被执行的字类型。 根据字类型，解码电路将控制脉冲施加到处理器时钟以使得ti产生三个可用周期长度中选择的一个或所述三个可用周期长度中的两个的组合。 以这种方式，系统性能得到显着改善。

    APPARATUS FOR SUSPENDING A SYSTEM CLOCK WHEN AN INITIAL ERROR OCCURS
    5.
    发明专利
    APPARATUS FOR SUSPENDING A SYSTEM CLOCK WHEN AN INITIAL ERROR OCCURS 未知

    公开(公告)号：CA1208800A

    公开(公告)日：1986-07-29

    申请号：CA454741

    申请日：1984-05-18

    Applicant: IBM

    Inventor： HOWE LELAND D JR ,  OZA BHARATKUMAR J ,  ROCHE THOMAS J

    IPC: G06F11/00 ,  G06F1/04 ,  G06F11/07

    Abstract: An apparatus disposed within a computer system is disclosed for sensing the existence of an error occurring within a computer system and for suspending an internal system clock when a certain number of clock pulses are generated following the occurrence of the error. When the internal system clock is suspended, operation of the computer system stops. In the preferred embodiment, the internal system clock is suspended when two (2) clock pulses are generated following the occurrence of the error. As a result, it is not necessary to wait until execution of the current instruction is complete before stopping the operation of the computer system. Therefore, other errors are not generated within the computer system as a result of the generation of the initial error.

    CLOCK PULSE GENERATOR WITH SELECTIVE PULSE DELAY AND PULSE WIDTH CONTROL
    6.
    发明专利
    CLOCK PULSE GENERATOR WITH SELECTIVE PULSE DELAY AND PULSE WIDTH CONTROL 未知

    公开(公告)号：CA1100195A

    公开(公告)日：1981-04-28

    申请号：CA309373

    申请日：1978-08-15

    Applicant: IBM

    Inventor： HOWE LELAND D JR ,  PANICCIA ALBERT E ,  SCOTTO VINCENT A

    IPC: G06F1/06 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  H03K5/06 ,  H03K5/13 ,  H04L7/00 ,  H03K1/18

    Abstract: CLOCK PULSE GENERATOR WITH SELECTIVE PULSE DELAY AND PULSE WIDTH CONTROL Clock generating apparatus for a computer system has selective pulse delay and pulse width control. Selection of pulse delay and pulse width is accomplished by loading registers with predetermined data patterns. The registers can be loaded under program control or by data entry units, such as a keyboard, switches, etc. The registers are located in coarse land fine pulse delay and pulse width adjustment units. These units have the same physical structure, but are functionally definable by a settable control element. A dither delay element is included in these coarse and fine adjustment units, and it is selectable to provide a small increment of delay. The coarse pulse delay and pulse width adjustment units also include pulse mode control circuitry to control operation in either normal oscillator mode or in single cycle mode.

    7.
    发明专利
    未知

    公开(公告)号：FR2412205A1

    公开(公告)日：1979-07-13

    申请号：FR7832878

    申请日：1978-11-16

    Applicant: IBM

    Inventor： HOWE LELAND D JR ,  PANICCIA ALBERT E ,  SCOTTO VINCENT A

    IPC: G06F1/04 ,  G06F1/08 ,  G06F1/06 ,  G06F1/10 ,  H03K5/06 ,  H03K5/13 ,  H04L7/00 ,  H03K1/18

    Abstract: Clock generating apparatus for a computer system has selective pulse delay and pulse width control. Selection of pulse delay and pulse width is accomplished by loading registers with predetermined data patterns. The registers can be loaded under program control or by data entry units, such as a keyboard, switches, etc. The registers are located in coarse and fine pulse delay and pulse width adjustment units. These units have the same physical structure, but are functionally definable by a settable control element. A dither delay element is included in these coarse and fine adjustment units, and it is selectable to provide a small increment of delay. The coarse pulse delay and pulse width adjustment units also include pulse mode control circuitry to control operation in either normal oscillator mode or in single cycle mode.

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