公开(公告)号：FR2295646A1

公开(公告)日：1976-07-16

申请号：FR7533886

申请日：1975-10-31

Applicant: IBM

Inventor： BUCKLEY FREDERICK III ,  CREAMER MALCOLM K JR ,  MILLER GERALD A ,  SCOTTO VINCENT A

IPC: H03K19/0185 ,  H03K5/02 ,  H03K17/687 ,  H03K19/017 ,  H03K19/08 ,  H03K19/0948

公开(公告)号：CA1100195A

公开(公告)日：1981-04-28

申请号：CA309373

申请日：1978-08-15

Applicant: IBM

Inventor： HOWE LELAND D JR ,  PANICCIA ALBERT E ,  SCOTTO VINCENT A

IPC: G06F1/06 ,  G06F1/04 ,  G06F1/08 ,  G06F1/10 ,  H03K5/06 ,  H03K5/13 ,  H04L7/00 ,  H03K1/18

Abstract: CLOCK PULSE GENERATOR WITH SELECTIVE PULSE DELAY AND PULSE WIDTH CONTROL Clock generating apparatus for a computer system has selective pulse delay and pulse width control. Selection of pulse delay and pulse width is accomplished by loading registers with predetermined data patterns. The registers can be loaded under program control or by data entry units, such as a keyboard, switches, etc. The registers are located in coarse land fine pulse delay and pulse width adjustment units. These units have the same physical structure, but are functionally definable by a settable control element. A dither delay element is included in these coarse and fine adjustment units, and it is selectable to provide a small increment of delay. The coarse pulse delay and pulse width adjustment units also include pulse mode control circuitry to control operation in either normal oscillator mode or in single cycle mode.

公开(公告)号：FR2412205A1

公开(公告)日：1979-07-13

申请号：FR7832878

申请日：1978-11-16

Applicant: IBM

Inventor： HOWE LELAND D JR ,  PANICCIA ALBERT E ,  SCOTTO VINCENT A

IPC: G06F1/04 ,  G06F1/08 ,  G06F1/06 ,  G06F1/10 ,  H03K5/06 ,  H03K5/13 ,  H04L7/00 ,  H03K1/18

Abstract: Clock generating apparatus for a computer system has selective pulse delay and pulse width control. Selection of pulse delay and pulse width is accomplished by loading registers with predetermined data patterns. The registers can be loaded under program control or by data entry units, such as a keyboard, switches, etc. The registers are located in coarse and fine pulse delay and pulse width adjustment units. These units have the same physical structure, but are functionally definable by a settable control element. A dither delay element is included in these coarse and fine adjustment units, and it is selectable to provide a small increment of delay. The coarse pulse delay and pulse width adjustment units also include pulse mode control circuitry to control operation in either normal oscillator mode or in single cycle mode.