公开(公告)号：DE60212962D1

公开(公告)日：2006-08-17

申请号：DE60212962

申请日：2002-05-15

Applicant: IBM

Inventor： CHEN HAO ,  HSU LU-CHEN ,  WANG LI-KONG

IPC: G01R31/28 ,  G06F11/27 ,  G01R31/3187 ,  G06F11/22 ,  H01L21/822 ,  H01L27/04

Abstract: Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.

公开(公告)号：DE60212962T2

公开(公告)日：2007-01-04

申请号：DE60212962

申请日：2002-05-15

Applicant: IBM

Inventor： CHEN HAO ,  HSU LU-CHEN ,  WANG LI-KONG

IPC: G01R31/28 ,  G06F11/27 ,  G01R31/3187 ,  G06F11/22 ,  H01L21/822 ,  H01L27/04

Abstract: Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.