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    HIERARCHICAL BUILT-IN SELF-TEST FOR SYSTEM-ON-CHIP DESIGN
    1.
    发明申请
    HIERARCHICAL BUILT-IN SELF-TEST FOR SYSTEM-ON-CHIP DESIGN 审中-公开
    系统级芯片设计的分层建立自检

    公开(公告)号：WO02095586A3

    公开(公告)日：2003-10-16

    申请号：PCT/GB0202302

    申请日：2002-05-15

    Applicant: IBM ,  IBM UK

    Inventor： CHEN HOWARD HAO ,  HSU LOUIS LU-CHEN ,  WANG LI-KONG

    IPC: G01R31/28 ,  G06F11/22 ,  G06F11/27 ,  H01L21/822 ,  H01L27/04 ,  G01R31/3187

    CPC classification number: G06F11/27

    Abstract: Hierarchical built-in self-test methods and arrangement for verifying system functionality. As a result, an effective built-in self-test methodology is provided for conducting complete system-on-chip testing, to ensure both the circuit reliability and performance of system-on-chip design. As an added advantage, development costs are reduced for system-on-chip applications.

    Abstract translation: 分层内置的自检方法和安排来验证系统功能。 因此，提供了一种有效的内置自检方法，用于进行完整的片上系统测试，以确保系统级芯片设计的电路可靠性和性能。 作为一个额外的优势，系统级芯片应用程序的开发成本有所降低。

    METHOD OF MANUFACTURING POLYMER CONDUCTING WIRE AND INTEGRATED CIRCUIT STRUCTURE
    2.
    发明专利
    METHOD OF MANUFACTURING POLYMER CONDUCTING WIRE AND INTEGRATED CIRCUIT STRUCTURE 审中-公开

    公开(公告)号：JP2003133317A

    公开(公告)日：2003-05-09

    申请号：JP2002193642

    申请日：2002-07-02

    Applicant: IBM

    Inventor： CLEVENGER LAWRENCE A ,  LOUIS L SHEW ,  RADENS CARL J ,  WANG LI-KONG ,  WONG KEITH KWONG HON

    IPC: G03F7/40 ,  H01B13/00 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/52 ,  H05K3/02

    Abstract: PROBLEM TO BE SOLVED: To provide a more simplified substitutional method of the conventional damascene approach. SOLUTION: The cloisonne approach includes a step of coating a semiconductor substrate with a photosensitive polymer, such as pyrrole having a silver salt, aniline, etc. A conductive polymer is exposed to a wet developing solution, by using standard photolithography and the resists developing method and only conductive polymer wires are left on a substrate by removing part of the exposed conductive polymer region. Then an insulating dielectric layer is adhered to the whole structure, and conductive polymer wires are produced by planarizing an insulator by the chemical mechanical polishing (CMP). Another embodiment of this invention includes a method and structure for a self- planarizing interconnecting material containing the conductive polymer. Consequently, the number of treating steps can be reduced, as compared with the conventional technology.

    Method for fabricating silicon device on sapphire by wafer bonding
    3.
    发明专利
    Method for fabricating silicon device on sapphire by wafer bonding 审中-公开
    通过波形焊接在硅胶上制备硅器件的方法

    公开(公告)号：JP2003031781A

    公开(公告)日：2003-01-31

    申请号：JP2002132064

    申请日：2002-05-07

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： HSU LOUIS L ,  SHI LEATHEN ,  WANG LI-KONG

    IPC: H01L27/12 ,  H01L21/02 ,  H01L21/762

    CPC classification number: H01L21/76256

    Abstract: PROBLEM TO BE SOLVED: To provide a method for fabricating a microwave circuit and a radio frequency circuit in a silicon on a sapphire substrate.
    SOLUTION: An improved method for fabricating a silicon on sapphire structure and/or device is disclosed. In one suitable embodiment, a single silicon oxide layer is interposed between a silicon layer and a sapphire layer by attaching the silicon oxide layer onto the silicon layer through growth or deposition and then attaching the sapphire layer to the oxide layer through wafer bonding. In another embodiment, a first silicon oxide layer is attached to the silicon layer through growth or deposition. Subsequently, a second silicon oxide layer is attached to the sapphire layer by deposition, for example. Thereafter, the first silicon oxide layer and the second silicon oxide layer are bonded by wafer bonding technology.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：提供一种在蓝宝石衬底上的硅中制造微波电路和射频电路的方法。 解决方案：公开了一种用于制造蓝宝石结构和/或器件上的硅的改进方法。 在一个合适的实施例中，通过生长或沉积将硅氧化物层附着在硅层上，然后通过晶片接合将蓝宝石层附着到氧化物层，将硅单层氧化硅层介于硅层和蓝宝石层之间。 在另一个实施例中，通过生长或沉积将第一氧化硅层附着到硅层。 随后，例如通过沉积将第二氧化硅层附着到蓝宝石层。 此后，通过晶片接合技术将第一氧化硅层和第二氧化硅层接合。

    Frequency change technique for adjusting operating frequency to compensate for aging electronic component
    4.
    发明专利
    Frequency change technique for adjusting operating frequency to compensate for aging electronic component 有权
    用于调整操作频率以补偿老化电子部件的频率变化技术

    公开(公告)号：JP2005063414A

    公开(公告)日：2005-03-10

    申请号：JP2004203829

    申请日：2004-07-09

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： KNEBEL DANIEL R ,  REOHR WILLIAM ROBERT ,  WANG LI-KONG

    IPC: G06F1/04 ,  G06F11/00 ,  G06F19/00

    CPC classification number: G06F11/008

    Abstract: PROBLEM TO BE SOLVED: To provide a frequency change technique that adjusts an operating frequency of an electronic system to compensate for one or more aging electronic components. SOLUTION: A number of performance parameters for an electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to a maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. The operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters can include prior operating frequencies, hours of operation, ambient temperature, and supply voltage. COPYRIGHT: (C)2005,JPO&NCIPI

    Abstract translation: 要解决的问题：提供一种调整电子系统的工作频率以补偿一个或多个老化的电子部件的频率变化技术。

    解决方案：在电子系统的特定年龄确定电子系统的许多性能参数。 性能参数可以与电子系统的特定年龄的电子系统的电子部件的最大工作频率相关。 根据性能参数调整电子元件的工作频率。 性能参数可以包括以前的工作频率，工作时间，环境温度和电源电压。 版权所有（C）2005，JPO＆NCIPI

    THIN FILM TRANSISTOR DEVICE, AND THEIR FORMING METHOD
    7.
    发明专利
    THIN FILM TRANSISTOR DEVICE, AND THEIR FORMING METHOD 审中-公开

    公开(公告)号：JP2003229435A

    公开(公告)日：2003-08-15

    申请号：JP2003003523

    申请日：2003-01-09

    Applicant: IBM

    Inventor： TORISHIA L BREEN ,  CLEVENGER LAWRENCE A ,  LEWIS L SUU ,  WANG LI-KONG ,  WONG KWONG HON

    IPC: H01L51/05 ,  H01L21/00 ,  H01L21/336 ,  H01L29/786 ,  H01L35/24 ,  H01L51/00 ,  H01L51/40

    Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for a flattened polymer transistor, and a structure thereof. SOLUTION: A completely flattened polymer thin film transistor is formed by processing a first portion of a device including a gate, a source, and a body element using a first flattened carrier. The thin film transistor is preferably formed with an organic material. For a gate dielectric a high K polymer can be employed to improve device performance. Then, a partly completed device structure is upside down, and is transferred to a second flattened carrier. A layer of wax or of a photosensitive organic material is deposited and is employed as a tentative bonding agent. A device including a body region is defined with an etching process. A contact to the device is formed with deposition of a conductive material and chemical/mechanical polishing. COPYRIGHT: (C)2003,JPO

    NEW MICROCELL REDUNDANCY SYSTEM FOR HIGH PERFORMANCE eDRAM
    8.
    发明专利
    NEW MICROCELL REDUNDANCY SYSTEM FOR HIGH PERFORMANCE eDRAM 有权
    用于高性能eDRAM的新型MICROCELL REDUNDANCY系统

    公开(公告)号：JP2003007084A

    公开(公告)日：2003-01-10

    申请号：JP2002116365

    申请日：2002-04-18

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

    Inventor： LOUIS L SHEW ,  WANG LI-KONG

    IPC: G06F12/08 ,  G06F12/16 ,  G11C11/401 ,  G11C29/00 ,  G11C29/04 ,  G11C29/24

    CPC classification number: G11C29/808 ,  G11C29/24 ,  G11C2207/104

    Abstract: PROBLEM TO BE SOLVED: To provide a new microcell redundancy system for a wide band width embedded DRAM having a SRAM cache interface.
    SOLUTION: For each bank of microcell array units comprising the eDRAM, at least one microcell unit is prepared as the redundancy to replace a defected microcell within the bank. After array testing, any defective microcell inside the bank is replaced with a redundancy microcell for that bank. A fuse bank structure implementing a lookup table is established for recording each redundant microcell address and its corresponding repaired microcell address. In order to allow simultaneous multi-bank operation, the redundant microcells may only replace the defective microcells within the same bank.
    COPYRIGHT: (C)2003,JPO

    Abstract translation: 要解决的问题：为具有SRAM缓存接口的宽带宽嵌入式DRAM提供新的微单元冗余系统。 解决方案：对于包含eDRAM的每个微单元阵列单元组，至少准备一个微单元单元作为冗余来代替存储体内的缺陷微单元。 在阵列测试之后，银行内的任何有缺陷的微单元被替换为该银行的冗余微单元。 建立实现查找表的熔丝库结构，用于记录每个冗余的微单元地址及其对应的修复的微单元地址。 为了允许同时多行操作，冗余微单元可以仅替换同一个存储体内的有缺陷的微单元。

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