公开(公告)号：JP2004280744A

公开(公告)日：2004-10-07

申请号：JP2003074834

申请日：2003-03-19

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： INAGAKI TATSUSHI ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/443

Abstract: PROBLEM TO BE SOLVED: To solve the problem that in requiring resisters of a number exceeding an analyzed number, the necessary register number consequently exceeds the register number provided in a computer, operation must be performed by using a memory lower in speed than the registers with poor efficiency.
SOLUTION: This compiler device for optimizing a program comprises an order limitation information acquisition part for acquiring order limitation information determined between a plurality of instructions of the program; an order determination part for successively determining the execution order of executing each instruction based on the order limitation information; a register number analysis part for analyzing the necessary register number that is the number of registers needed in execution of the instructions with determined execution orders; an instruction detection part for detecting a combination of two instructions, one order being an order-determined instruction, and the other order being an order non-determined instruction, in which an order limitation for executing the one instruction prior to the other instruction is not included in the order limitation information; and an order determination reprocessing part for changing, when the necessary register number exceeds a predetermined number, the one instruction to a state where no execution order is determined and determining the execution orders so as to execute the one command after the other command.
COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2004355279A

公开(公告)日：2004-12-16

申请号：JP2003151478

申请日：2003-05-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： INAGAKI TATSUSHI ,  ONODERA TAMIYA ,  KOMATSU HIDEAKI

IPC: G06F9/45

Abstract: PROBLEM TO BE SOLVED: To enable a code conversion device 10 for converting a code to be converted such as a Java byte code into a machine language code to generate the machine language code associated with effective prefetch. SOLUTION: Under the consideration of a pointer reference load instruction in each iteration of a loop on a program and a data dependent load instruction with respect to the pointer reference load instruction in each iteration, first and second detecting means 17 and 18 check inter-iteration and in-iteration strides associated with the pointer reference load instruction and the data dependent load instruction by performing access to a heap memory 19. First and second machine language code part generating means generate a predetermined machine language code part on the basis of the inter-iteration and in-iteration constant strides set by a setting means 22. As a result, in machine language code execution, data associated with the data dependent load instruction are effectively prefetched from a heap memory 13 to a cache memory. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2001075814A

公开(公告)日：2001-03-23

申请号：JP23253399

申请日：1999-08-19

Applicant: IBM

Inventor： KOSEKI SATOSHI ,  INAGAKI TATSUSHI ,  YASUE TOSHIAKI ,  KOMATSU HIDEAKI ,  TAKEUCHI MIKIO

IPC: G06F9/45

Abstract: PROBLEM TO BE SOLVED: To effectively optimize an object code in the range satisfying limitation caused by the number of physical registers of a processor. SOLUTION: This compiler device performs code generation from a program represented by a DAG(directed acyclic graph) while evaluating the number of used registers and the number of execution cycles and optimizes a code to be generated. That is, the compiler calculates the number of cycles with which each operation can be executed on the DAG and the number of the currently available registers, performs code generation while preceding an operator on an execution path that takes the most time in the DAG in a part where the number of registers is sufficient, and performs code generation while preceding such an operator as to reduce the number of used registers when the number of registers is not sufficient.

公开(公告)号：JP2010061522A

公开(公告)日：2010-03-18

申请号：JP2008228286

申请日：2008-09-05

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： NAKAIKE TAKUYA ,  INAGAKI TATSUSHI ,  OGASAWARA TAKESHI ,  SUGANUMA TOSHIO

IPC: G06F9/46 ,  G06F9/52 ,  G06F12/00

CPC classification number: G06F9/526 ,  G06F9/3004 ,  G06F9/30087

Abstract: PROBLEM TO BE SOLVED: To provide a mechanism for stopping only a thread in which a fault is caused or a fault may be caused from another thread without stopping the whole system having a locked thread. SOLUTION: A computer system stores a program including a code for a critical section, wherein the critical section includes an instruction for writing or reading a value to/from a shared data area in a memory. The instruction acquires lock for the critical section before the start of an initial instruction in the critical section, writes a value in a thread local area in the memory instead of writing the value in the shared data area in response to a writing instruction to the shared data area, writes the value written in the thread local area in the shared data area in response to the end of a final instruction in the critical section, and unlocks the critical section. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种仅停止引起故障的线程或者可能由另一线程引起故障而不停止具有锁定线程的整个系统的机构。 解决方案：计算机系统存储包括关键部分的代码的程序，其中临界部分包括用于向/从存储器中的共享数据区域写入或读取值的指令。 该指令在关键部分中的初始指令开始之前获取关键部分的锁定，将值写入存储器中的线程局部区域中，而不是响应于对共享的写入指令将数据写入共享数据区域中 数据区域，响应于关键部分中的最终指令的结束，写入共享数据区域中的线程局部区域中写入的值，并解锁关键部分。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2009059001A

公开(公告)日：2009-03-19

申请号：JP2007223143

申请日：2007-08-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： OHIRA REI ,  INAGAKI TATSUSHI ,  NAKAIKE TAKUYA ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/441

Abstract: PROBLEM TO BE SOLVED: To reduce variables not to be allocated to registers, reduce transfer of value between registers, and improve efficiency in executing a program. SOLUTION: A compiler device stores interference information indicating an interference relation between variables, selects a register according to a predetermined procedure from a reference number or more of the registers so that the same register is not allocated to the set of variables having the interference relation, allocates the register to each of the respective variables, substitutes the plurality of variables allocated to the same register with new variables, merges the interference relations for each of the plurality of variables, generates an interference relation for the new variables, updates the interference information according to the interference relation, and allocates a register selected from the reference number or more of registers according to a procedure same as the predetermined procedure to each of the variables in the program that uses the new variables so that the same register is not allocated to a set of certain variables having an interference relation based on the updated interference information. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：为了减少不分配给寄存器的变量，减少寄存器之间的值传输，并提高执行程序的效率。 解决方案：编译器设备存储指示变量之间的干扰关系的干扰信息，根据预定过程从参考数量或更多个寄存器中选择寄存器，使得相同的寄存器不分配给具有 干扰关系，将寄存器分配给每个变量，将分配给同一寄存器的多个变量替换为新变量，合并多个变量中的每一个的干扰关系，生成新变量的干扰关系，更新 根据干扰关系的干扰信息，并且根据与预定过程相同的过程从参考数量或更多个寄存器中选择的寄存器分配给使用新变量的程序中的每个变量，使得相同的寄存器不是 分配给具有干扰关系的一组变量 基于更新的干扰信息。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2003280919A

公开(公告)日：2003-10-03

申请号：JP2002069221

申请日：2002-03-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： ISHIZAKI KAZUAKI ,  INAGAKI TATSUSHI ,  KOMATSU HIDEAKI

IPC: G06F9/45

CPC classification number: G06F8/445

Abstract: PROBLEM TO BE SOLVED: To perform instruction movement for speculative execution while securing shortening of execution time to exception dependence for hardware- initiated potentially exception instructions (H-PEI) and software-initiated potentially exception instructions (S-PEI) inserted before the H-PEI, in a device which compiles a program described in a type safe language such as Java. SOLUTION: A dependence graph discriminating an exception dependent arc from other dependence arcs such as a control dependence arc or a data dependence arc is created. As to the fastest execution start time of H-PEI, it is examined which case is faster, execution through the exception dependence arc or execution not through the exception dependence arc. If the latter case is faster, the instruction movement for the speculative execution for the instruction sequence including the H-PEI is performed. COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：执行指令移动以推测执行，同时确保将执行时间缩短到针对硬件启动的潜在异常指令（H-PEI）和软件启动的潜在异常指令（S-PEI）的异常依赖 H-PEI，在编译以类型安全语言（如Java）描述的程序的设备中。 解决方案：创建一个依赖图来区分异常依赖弧与其他依赖弧，如控制相关弧或数据相关弧。 对于H-PEI的最快执行开始时间，检查哪种情况更快，通过异常依赖弧执行或不通过异常依赖弧执行。 如果后一种情况较快，则执行用于包括H-PEI的指令序列的推测执行的指令移动。 版权所有（C）2004，JPO

公开(公告)号：JP2002149416A

公开(公告)日：2002-05-24

申请号：JP2000331427

申请日：2000-10-30

Applicant: IBM

Inventor： INAGAKI TATSUSHI ,  KOMATSU HIDEAKI

IPC: G06F9/38 ,  G06F9/45

Abstract: PROBLEM TO BE SOLVED: To make effectively obtainable the instruction level parallelism of a program including an exception generable instruction by relaxing the preceding constraint of the exception generation validation instruction to the other instruction like software. SOLUTION: This compiler is provided with a DAG generating part 21 for generating a DAG by analyzing the four sets of intermediate codes of a program to be processed, a DAG editing part 22 for editing the generated DAG, and relaxing the sequence constraint of operators due to exceptions, and a four set of intermediate code reproducing part 23 for generating the four sets of intermediate codes on which the structure of the edited DAG is reflected. Then, an exception generable instruction and an exception generation detection instruction are detected from the DAG, and the detected exception generation detection instruction is divided into a first instruction for detecting the generation condition of exceptions and a second instruction for conditionally branching the processing to the exception processing. Then, dependency is set so that when the generation condition of the exceptions is detected in response to the first instruction, its transition to the second instruction can be performed, and when the generation condition of exceptions is not detected, its transition to the exception generable instruction can be performed.

公开(公告)号：JP2000222219A

公开(公告)日：2000-08-11

申请号：JP1794399

申请日：1999-01-27

Applicant: IBM

Inventor： KOSEKI SATOSHI ,  INAGAKI TATSUSHI ,  KOMATSU HIDEAKI

IPC: G06F9/45 ,  G06F9/00 ,  G06F9/44 ,  G06F9/445 ,  G06F9/46 ,  G06F12/02

Abstract: PROBLEM TO BE SOLVED: To provide a method and device for processing a multidimensional array object capable of improving the processing speed of multidimensional disposition without the change of a specification. SOLUTION: The object of the processing method of this multidimensional array object is the processing method of the multidimensional object in a language (Java, e.g.) where the multidimensional array is realized by the array of array objects. The multidimensional array object consisting of the array object constituting the multidimensional array is added with a processing optimization possible flag showing that processing to the element of the multidimensional array can be optimized as additional information. The processing optimization possible flag is stored in a storing device (a main memory e.g.). After then, a machine code corresponding to the state of the processing optimization possible flag is executed.