公开(公告)号：CH607462A5

公开(公告)日：1978-12-29

申请号：CH650276

申请日：1976-05-24

Applicant: IBM

Inventor： FREEMAN LEO BOYES ,  INCERTO ROBERT JAMES ,  PETROSKY JOSEPH ANTHONY JR

IPC: G11C11/412 ,  H01L21/8236 ,  H01L27/088 ,  H01L29/78 ,  H03K3/356 ,  H03K17/00 ,  H03K17/041 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/21 ,  H03K19/08 ,  H01L27/04

Abstract: A circuit comprising the parallel connection of an enhancement-and a depletion-type FET which exhibits reduced power and improved performance for both logic as well as memory circuits.

公开(公告)号：DE2608576A1

公开(公告)日：1976-09-30

申请号：DE2608576

申请日：1976-03-02

Applicant: IBM

Inventor： FREEMAN JUN LEO BOYES ,  INCERTO ROBERT JAMES ,  PETROSKY JOSEPH ANTHONY

IPC: H03F3/343 ,  H03F3/34 ,  H03F3/45 ,  H03K17/687 ,  H03K19/0175 ,  H03F3/16

Abstract: A dual channel high gain differential amplifier utilizing enhancement depletion MOS field effect transistors which exhibits high common mode rejection and fast switching characteristics.

公开(公告)号：DE2721851A1

公开(公告)日：1978-01-05

申请号：DE2721851

申请日：1977-05-14

Applicant: IBM

Inventor： FREEMAN LEO BOYES ,  INCERTO ROBERT JAMES ,  PETROSKY JUN JOSEPH ANTHONY

IPC: G11C11/41 ,  G11C11/409 ,  G11C11/419 ,  H03K3/356 ,  G11C7/06 ,  G11C11/40

Abstract: Disclosed is a self-isolating cross-coupled sense amplifier latch circuit having five enhancement mode field effect transistor devices and two depletion mode field effect transistor devices. The first and second field effect transistors form a cross-coupled pair with true and complement outputs being available at the cross-coupled nodes. A third field effect transistor is connected to a common connection between the source electrodes of the cross-coupled pair and is used to establish a race condition after a small difference in potential has been applied to the aforementioned output nodes. A pair of depletion mode devices are connected as diodes between a positive potential (VH) and each of the output nodes, respectively. Each of the output nodes is connected to a respective bit line of a column of memory cells through enhancement mode field effect transistors connected as third and fourth unidirectionally conducting devices.

公开(公告)号：AU1465076A

公开(公告)日：1977-12-08

申请号：AU1465076

申请日：1976-06-04

Applicant: IBM

Inventor： FREEMAN LEO BOYES ,  INCERTO ROBERT JAMES ,  PETROSKY JOSEPH ANTHONY JR

IPC: G11C11/412 ,  H01L21/8236 ,  H01L27/088 ,  H01L29/78 ,  H03K3/356 ,  H03K17/00 ,  H03K17/041 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/21 ,  H03K19/08 ,  H03K19/32 ,  H01L29/80 ,  H01L27/06 ,  G11C11/40 ,  H03K19/30 ,  H03K19/24

Abstract: A circuit comprising the parallel connection of an enhancement-and a depletion-type FET which exhibits reduced power and improved performance for both logic as well as memory circuits.

公开(公告)号：DE2623507A1

公开(公告)日：1976-12-09

申请号：DE2623507

申请日：1976-05-26

Applicant: IBM

Inventor： FREEMAN LEO BOYES ,  INCERTO ROBERT JAMES ,  PETROSKY JUN JOSEPH ANTHONY

IPC: G11C11/412 ,  H01L21/8236 ,  H01L27/088 ,  H01L29/78 ,  H03K3/356 ,  H03K17/00 ,  H03K17/041 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/0944 ,  H03K19/21 ,  H03K19/08 ,  G11C7/00 ,  G11C11/40 ,  H01L27/08

Abstract: A circuit comprising the parallel connection of an enhancement-and a depletion-type FET which exhibits reduced power and improved performance for both logic as well as memory circuits.