公开(公告)号：BR7304906D0

公开(公告)日：1974-08-29

申请号：BR490673

申请日：1973-07-02

Applicant: IBM

Inventor： RISEMAN J ,  IRVING TZE HO

IPC: G06F12/08 ,  B23D45/00 ,  G06F13/00 ,  G11B20060101 ,  G11C7/00 ,  G11C11/00 ,  G11C11/40

公开(公告)号：CH508964A

公开(公告)日：1971-06-15

申请号：CH1632970

申请日：1970-11-04

Applicant: IBM

Inventor： JOSEPH JUIFU CHANG ,  IRVING TZE HO ,  NORBERT GEORGE JR VOGL ,  PEIG FENG WU BEVAN

IPC: G11C11/411 ,  H01L21/74 ,  H01L27/07 ,  H03K3/288 ,  G11C11/40 ,  H01L19/00

公开(公告)号：IT1164517B

公开(公告)日：1987-04-15

申请号：IT2680779

申请日：1979-10-26

Applicant: IBM

Inventor： IRVING TZE HO ,  RISEMAN JACOB

IPC: H01L29/73 ,  H01L21/033 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/331 ,  H01L21/336 ,  H01L21/76 ,  H01L21/762 ,  H01L29/10 ,  H01L29/78 ,  H01L

公开(公告)号：IT1164518B

公开(公告)日：1987-04-15

申请号：IT2680879

申请日：1979-10-26

Applicant: IBM

Inventor： IRVING TZE HO ,  RISEMAN JACOB

IPC: H01L21/22 ,  H01L21/033 ,  H01L21/225 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/331 ,  H01L21/336 ,  H01L29/78 ,  H01L

公开(公告)号：IT8021316D0

公开(公告)日：1980-04-11

申请号：IT2131680

申请日：1980-04-11

Applicant: IBM

Inventor： IRVING TZE HO ,  JACOB RISEMAN

IPC: H01L27/10 ,  G11C11/35 ,  G11C11/404 ,  H01L21/31 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/78 ,  G11C

Abstract: A method for making highly dense, dielectrically isolated, U-shaped MOSFET. In a preferred method a monocrystalline silicon P substrate with a N+ layer thereon, a P layer on the N+ layer and a N+ layer on the P layer is provided. A pattern of U-shaped openings is formed in the body through to the P substrate by the reactively ion etching technique. This pattern of openings is filled with an insulator material, such as silicon dioxide. A conductive layer of N+ doped polycrystalline silicon is deposited on the bare surface of this silicon body. Openings are formed in the polycrystalline silicon over the silicon dioxide filled openings. A silicon dioxide layer is then grown by, for example, thermal oxidation over the polycrystalline silicon layer. Reactively ion etching is used to produce substantially U-shaped openings through the layers over the P substrate and into the P substrate to substantially bisect the regions of monocrystalline silicon. This etching step forms two storage cells in the monocrystalline silicon areas and a bit line for each column of cells in the polycrystalline silicon layer. A silicon dioxide gate insulator is grownon the monocrystalline silicon surfaces of the U-shaped openings by thermal oxidation in a suitable ambient. Conductively doped polycrystalline silicon is deposited in the U-shaped openings over the silicon dioxide gate insulator layer until the openings are filled and cover the surface of the body. The conductively doped polycrystalline silicon on the surface of the body is etched in a suitable pattern to produce the word lines of the random access memory device.