Abstract:
PROBLEM TO BE SOLVED: To provide a DMA controller capable of responding to a number of transfer modes without using a complicated transfer engine. SOLUTION: This controller comprises a preprocessor 32, which generates an instruction packet according to a transfer mode and gives it to a memory/peripheral device transfer engine 18 and a peripheral device/memory transfer engine 20. The instruction packet includes a transfer direction identification parameter, a transfer start memory address, an address increase/decrease flag, a tag identification flag, a tag transfer identification flag and a transfer word number. The transfer engines 18 and 20 transfer data between a memory and a peripheral device according to the instruction packet. COPYRIGHT: (C)2007,JPO&INPIT
Abstract:
PROBLEM TO BE SOLVED: To provide a processor device having the upward compatibility of a USB1.1 without impairing the transfer speed of a USB2.0. SOLUTION: This processor device 10 is provided with: a CPU 12; a memory 14; a PLB 16; a main OPB 20; a PLB-to-OPB bridge 24; an OPB-to-PLB bridge 26; an OPB master/slave device 30; an OPB slave device 32; a sub-OPB 46; an OPB-to-PLB bridge 50: a main AHB 52; an OPB-to-AHB bridge 58; a sub-AHB 60; an AHB-to-OPB bridge 66; and a USB2.0 host controller 40. The host controller 40 is provided with an EHCI42 for a USB2.0 and an OHCI44 for a USB1.1. Bus slave parts 68 and 72 of the EHCI42 and the OHCI44 are connected to the main AHB52, and the bus master parts 70 and 74 are connected to the sub-AHB 52. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract:
PURPOSE: To generate the dot clock of a liquid crystal display device from a horizontal synchronizing signal with little skew. CONSTITUTION: The function of PSS is divided into three. One of them is means 29, 36 and 34 for obtaining a specific frequency. These means supply voltage to VCO 30 from DAC(digital-analog converter) 29 of a latch type. The horizontal synchronizing signal is inversely calculated from a finally generated dot clock to increase/reduce the value of DAC 29 based on an error between this calculated horizontal synchronizing signal and an actual horizontal synchronizing signal. Correction by this increase/reduction is executed with the timing of vertical synchronization, e.g. The second one of the function is a synchronizing means 34 which adds a signal corresponding to an error between the actual horizontal synchronizing signal and the phase with a dot clock to a signal from DAC 29 to control the phase of the dot clock. Third one is PLL means 31 and 32 generating the dot clock based on the signal of the prescribed frequency.