公开(公告)号：JP2006309561A

公开(公告)日：2006-11-09

申请号：JP2005132242

申请日：2005-04-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ISHII KOJI

IPC: G06F13/28 ,  G06F13/36

CPC classification number: G06F13/28

Abstract: PROBLEM TO BE SOLVED: To provide a DMA controller capable of responding to a number of transfer modes without using a complicated transfer engine.
SOLUTION: This controller comprises a preprocessor 32, which generates an instruction packet according to a transfer mode and gives it to a memory/peripheral device transfer engine 18 and a peripheral device/memory transfer engine 20. The instruction packet includes a transfer direction identification parameter, a transfer start memory address, an address increase/decrease flag, a tag identification flag, a tag transfer identification flag and a transfer word number. The transfer engines 18 and 20 transfer data between a memory and a peripheral device according to the instruction packet.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供一种能够在不使用复杂的传输引擎的情况下响应多个传送模式的DMA控制器。 解决方案：该控制器包括预处理器32，该预处理器32根据传送模式生成指令包，并将其提供给存储器/外围设备传输引擎18和外围设备/存储器传输引擎20.指令包包括传送 方向识别参数，传送开始存储器地址，地址增加/减少标志，标签识别标志，标签传送识别标志和传送字号。 传输引擎18和20根据指令包在存储器和外围设备之间传送数据。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2006048256A

公开(公告)日：2006-02-16

申请号：JP2004226226

申请日：2004-08-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： TSUKAMOTO SOICHI ,  ISHII KOJI

IPC: G06F13/38

Abstract: PROBLEM TO BE SOLVED: To provide a processor device having the upward compatibility of a USB1.1 without impairing the transfer speed of a USB2.0.
SOLUTION: This processor device 10 is provided with: a CPU 12; a memory 14; a PLB 16; a main OPB 20; a PLB-to-OPB bridge 24; an OPB-to-PLB bridge 26; an OPB master/slave device 30; an OPB slave device 32; a sub-OPB 46; an OPB-to-PLB bridge 50: a main AHB 52; an OPB-to-AHB bridge 58; a sub-AHB 60; an AHB-to-OPB bridge 66; and a USB2.0 host controller 40. The host controller 40 is provided with an EHCI42 for a USB2.0 and an OHCI44 for a USB1.1. Bus slave parts 68 and 72 of the EHCI42 and the OHCI44 are connected to the main AHB52, and the bus master parts 70 and 74 are connected to the sub-AHB 52.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供具有USB1.1向上兼容性的处理器设备，而不损害USB2.0的传输速度。 解决方案：该处理器装置10设置有：CPU 12; 存储器14; 一架小巴16; 主要OPB 20; PLB到OPB桥24; OPB到PLB桥26; OPB主/从设备30; OPB从设备32; 一个次级方案组46; OPB到PLB桥50：主AHB 52; OPB至AHB桥58; 次AHB 60; AHB到OPB桥66; 以及USB2.0主机控制器40.主机控制器40具有用于USB2.0的EHCI42和用于USB1.1的OHCI44。 EHCI42和OHCI44的总线从站68和72连接到主AHB52，总线主站70和74连接到子AHB 52。版权所有（C）2006年，JPO＆NCIPI

公开(公告)号：JPH07110667A

公开(公告)日：1995-04-25

申请号：JP24509893

申请日：1993-09-30

Applicant: IBM

Inventor： MAMIYA TAKESHIGE ,  NISHINO HIROZO ,  ISHII KOJI

IPC: G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  H03L7/07 ,  H03L7/18 ,  H04N5/12 ,  H04N5/66

Abstract: PURPOSE: To generate the dot clock of a liquid crystal display device from a horizontal synchronizing signal with little skew. CONSTITUTION: The function of PSS is divided into three. One of them is means 29, 36 and 34 for obtaining a specific frequency. These means supply voltage to VCO 30 from DAC(digital-analog converter) 29 of a latch type. The horizontal synchronizing signal is inversely calculated from a finally generated dot clock to increase/reduce the value of DAC 29 based on an error between this calculated horizontal synchronizing signal and an actual horizontal synchronizing signal. Correction by this increase/reduction is executed with the timing of vertical synchronization, e.g. The second one of the function is a synchronizing means 34 which adds a signal corresponding to an error between the actual horizontal synchronizing signal and the phase with a dot clock to a signal from DAC 29 to control the phase of the dot clock. Third one is PLL means 31 and 32 generating the dot clock based on the signal of the prescribed frequency.